EEPROM memory organized in plural bit words

Details EEPROM memory organized in plural bit words EEPROM memory organized in plural bit words

1993-12-08

1995-07-11

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Complementing/balancing

365207, 365208, 365210, 327 52, G11C 700

Patent

active

054327466

ABSTRACT:
The invention relates to integrated circuit memories and more particularly to non-volatile memories of the EEPROM type. The memory is organized in p-bit words (p>1) with p-read circuits operating in a differential way with respect to a reference line. The memory operates with a balancing phase of the bit line and of the reference line prior to the actual read phase. The reference line is common to the p-read circuits and, for this purpose, a balancing circuit is provided in the read circuits, which acts without shorting the bit line and the reference line. Such circuit includes a follower amplifier in a feedback loop arrangement. The follower amplifier changes the bit line potential in a direction tending to null the output of a differential amplifier used for reading the memory cell state.

REFERENCES:
patent: 5321660 (1994-06-01), Sani et al.
IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988 New York, U.S., pp. 1150-1156, Gastaldi et al `A 1-Mbit CMOS EPROM with Enhanced Verification`.

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