Circuits, systems and methods for testing integrated circuit dev
CMOS cell and circuit design for improved IDDQ testing
CMOS memory margining control circuit for a nonvolatile memory
CMOS static RAM testability
Column redundancy circuit for a semiconductor memory device
Compressed input/output test mode
Computer memory with status cell
Configurable self-test for embedded RAMs
Configure registers and loads to tailor a multi-level cell...
Consumption current circuit and method for memory device
Contact test method and system for memory testers
Control apparatus for testing a random access memory
Controller for delay locked loop circuits
Core test control
Current mode test circuit for SRAM
Current saturation test device