Controller for delay locked loop circuits

Details Controller for delay locked loop circuits Controller for delay locked loop circuits

2002-08-29

2004-10-26

Le, Thong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S233100

Reexamination Certificate

active

06809974

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to integrated circuits, and in particular to a delay locked loop in a memory device during a test.
BACKGROUND OF THE INVENTION
Delay locked loops (DLLs) are often used in integrated circuits (ICs) to generate an internal clock signal. In a typical DLL, the internal clock signal is generated by applying an amount of delay to a system clock or an external clock signal. The DLL tracks the external and internal clock signals with a detect operation and adjusts the amount of delay with a shifting operation to keep the internal and external clock signals synchronized.
In some integrated circuit devices, such as dynamic random access memory (DRAM) devices, the internal clock signal generated by the DLL is normally used as a timing signal for certain operations of the memory device. For example, in some memory devices, the internal clock signal can be used as a clock signal to provide timing for data transfer to and from the memory device.
A traditional memory device has a number of memory cells for storing data. To store data into the memory cells, a WRITE operation is performed. To retrieve the stored data, a READ operation is performed. Typically, a WRITE or READ operation includes two separate modes, an ACTIVE mode followed by a WRITE or READ mode. In the ACTIVE mode, the memory device activates a so-called ACTIVE command signal to “open” or activate the memory cells in preparation for a subsequent WRITE or READ mode. Following the ACTIVE mode, if it is a READ operation, the memory device activates a so-called READ command signal to access the activated memory cells to read the stored data in the memory cells.
Typically, activating the memory cells during the ACTIVE mode or accessing the memory cells during the READ mode demands a higher than normal amount of current which causes the internal supply voltage of the memory device to drop. The drop in the internal supply voltage changes the voltage supplied to the DLL. The change in the voltage supplied to the DLL causes a change in the amount of delay applied to the external clock signal. The change in the amount of delay causes the external and internal clock signals to be out of synchronism. When the external and internal signals are out of synchronism, the DLL performs a shifting operation to adjust the amount of delay to compensate for the drop in voltage during the ACTIVE mode to eventually put the external and internal clock signals back to synchronism.
Although the external and internal clock signal are eventually synchronized after the ACTIVE mode, the shifting operation during the ACTIVE mode may put the DLL in an unknown condition, which may change the timing for the data transfer of the memory device and move the data output timing out of the specification requirement. This change in the timing may not provide satisfactory level of accuracy for the data transfer of the memory device especially for new generations of high speed memory devices.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need for a method to monitor the behavior of a DLL in an integrated circuit device such as a memory device during a test mode to determine the effect of the ACTIVE, READ or REFRESH mode on the DLL.
SUMMARY OF THE INVENTION
The present invention includes a method of characterizing a DLL during a memory test mode by activating a DLL control signal to disable a synchronization operation of the DLL during the test mode so that the behavior of the DLL can be monitored before and after the DLL control signal is activated.
In one aspect, a memory device is provided. The memory device includes a DLL for generating an internal clock signal based on an external clock signal. The DLL keeps the external and internal clock signals synchronized by performing a synchronization operation. The memory device further includes a DLL controller connected to the DLL. During the mode of the memory device, the DLL controller activates a DLL control signal to prevent the DLL from performing the synchronization operation.
In another aspect, a method of testing a DLL of memory device is provided, the method includes activating a test mode signal during a test mode. The method also includes activating a DLL control signal when the test mode signal is activated. The method further includes disabling the DLL with the DLL control signal such that the DLL does not perform a synchronization operation during the test mode, wherein the synchronization operation synchronizes an external clock signal and an internal clock signal.


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