Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-08-28
2001-09-25
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C714S718000
Reexamination Certificate
active
06295239
ABSTRACT:
The invention relates to control apparatus for testing a random access memory (RAM), and in particular, a RAM on a logic device.
Conventionally, there are a number ways of testing a RAM on a logic device. For example, it is possible to use a microcontroller, or other processor, on the logic device to test the RAM using a suitable test program.
Another method of testing is to use what is commonly known as built-in self test (BIST). This is implemented by building test logic onto the logic device. The only function of the test logic is to test the RAM.
However, with BIST, in order to generate the test algorithm, which is permanently stored in the test logic, it is essential to know the internal structure of the RAM to efficiently and comprehensively test the RAM. It is only possible to choose an appropriate test bit pattern to properly test the RAM if the internal structure of the RAM is known. The test bit pattern is fixed into the test logic on the logic device and therefore, cannot be altered. Hence, it is essential when designing the logic device to be able to generate the optimum test algorithm and test bit pattern using the test logic as there is no flexibility to be able to change the test algorithm or the test bit pattern after the logic device has been fabricated.
One of the problems with determining the internal structure of the RAM is that as the RAM is usually supplied by another manufacturer and then built onto the logic device, the internal structure of the RAM is generally not known. Therefore, it can be difficult or impossible to generate the optimum test algorithm and test bit pattern to build into the test logic to test the RAM.
In accordance with the present invention, control apparatus for testing a RAM comprises a control device coupled to an address generator, a data generator and a state machine, the state machine receiving outputs from the address generator, the data generator and the control device, and in response to the received outputs, outputting data, address and control signals, and a control interface coupled to the control device, the control interface being adapted to receive input signals and the control device being controlled in accordance with the input signals to control the data generator to generate data, the data generated being dependent on the input signals.
In accordance with a second aspect of the present invention, a method of performing a built-in self test of a RAM on a logic device comprises generating input signals and coupling the input signals to a control apparatus for testing a RAM, the input signals causing the control apparatus to generate a test bit pattern which is dependent on the input signals, the generated test bit pattern being transmitted to the RAM for storage at an address in the RAM and subsequently reading a test bit pattern stored at the address and comparing the test bit pattern with the bit pattern read from the address.
In accordance with a third aspect of the present invention, there is provided a logic device comprising a RAM and control apparatus, the control apparatus being adapted to receive input signals from a processor, and the control apparatus being coupled to the RAM to send signals to the RAM in response to the input signals received, and wherein the control apparatus comprises a data generator, the data generator generating a test bit pattern which is dependent on the received input signals.
An advantage of the invention is that by including control apparatus with a data generator and a control interface, it is possible to control the data generator to generate different test bit patterns to test the random access memory.
Typically, the control apparatus further comprises an address generator and a control generator to generate address and control signals for the RAM.
In one example of the invention, the logic device also comprises the processor from which the control apparatus receives the input signals. However, it is possible that the processor may be external from the logic device.
Typically, the logic device may further comprises a register device which monitors signals sent to the RAM by the control apparatus and received from the RAM by the control apparatus. Typically, the register device is coupled to an output contact on the logic device to permit the register device to be monitored by an external device. Preferably, the register device is a signature register device and most preferably, is a multiple input signature register device (MISR).
REFERENCES:
patent: 6009028 (1999-12-01), Akiyama
patent: 6151692 (2000-11-01), Smitlener et al.
Infineon Technologies A.G.
Le Vu A.
Senniger Powers Leavitt & Roedel
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