Gate Structure in flash memory cell and method of forming...
Gate structure of a semiconductor device
Gate structure with high K dielectric
Gate structure with independently tailored vertical doping...
Gate structures for flash memory and methods of making same
Gate structures having sidewall spacers using selective...
Gate structures having sidewall spacers using selective...
Gate structures with increased etch margin for self-aligned...
Gate technology for strained surface channel and strained...
Gate technology for strained surface channel and strained...
Gate technology for strained surface channel and strained...
Gate trim process using either wet etch or dry etch approach...
Gate with dual gate dielectric layer and method of...
Gate-all-around semiconductor device and process for...
Gate-all-around type of semiconductor device and method of...
Gate-contact structure and method for forming the same
Gate-controlled, graded-extension device for deep sub-micron...
Gate-controlled, negative resistance diode device using...
Gate-induced strain for MOS performance improvement
Gate/drain capacitance reduction for double gate-oxide DMOS with