Gate structures with increased etch margin for self-aligned...

Details Gate structures with increased etch margin for self-aligned... Gate structures with increased etch margin for self-aligned...

2000-04-26

2003-05-20

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S592000, C438S595000, C438S303000, C438S710000, C438S714000, C438S647000, C438S683000, C257S388000, C257S412000, C216S002000, C216S066000

Reexamination Certificate

active

06566236

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a method of manufacturing semiconductor devices and, more particularly, to contact formation.
2. Description of the Related Art
In conventional semiconductor manufacturing, after source/drain regions are formed along a side of gate structures, an interlevel insulating layer is deposited over the resultant structure. Contact holes are then formed in the interlevel insulating layer down to the source/drain regions in order to electrically connect with the source/drain regions. Subsequently, metal is deposited to fill the contact holes for interconnection. During formation, shorts between the contact fillings and the gate structures must be prevented to avoid device failures.
In recent years, aligning contact holes between closely spaced interconnects has become a dominant impediment to ever increasing density of ULSI (ultra large scale integration) circuits. Furthermore, as modern contact lithography technology approaches its limit, forming small contact holes within alignment tolerances has become quite difficult.
To alleviate these problems, SAC (self-aligned contact) technology has been developed. U.S. Pat. No. 5,831,899 assigned to Integrated Device Technology, Inc., the disclosure of which is incorporated herein by reference, illustrates such SAC technology.
SAC technology uses a selective etching process to form contact holes. SAC technology utilizes the fact that various materials used for semiconductor fabrication, such as silicon nitride, silicon dioxide, polysilicon and photoresist each have different etch removal rates during etching. An example of conventional SAC structure is shown in-
FIG. 1
A. The material used for spacers
12
and/or a capping layer
14
, e.g., silicon nitride, has a slower etch rate than the material used for an interlevel insulating layer
16
, e.g., silicon oxide. As a result, the contact holes
18
can be defined by using an etchant that etches away predetermined regions of the interlevel insulating layer between the gate structures at a faster rate than it etches the spacers
12
and/or the capping layers
14
. SAC technology thus generally enables the accurate formation of the contact holes even when the photoresist pattern defining the contact holes is not precisely aligned. During formation, the remaining amount of shoulder (shoulder remaining) or etch margin indicated as x and y in
FIG. 1A
, prevents shorts from occurring between contact plugs
20
and gate structures
22
.
Prior SAC technology is not flawless. For example, accidental shorts can still occur between gate structures and contact plugs. Due to the limits of current selective etching processes, some amount of unwanted etching can occur in the spacers or the capping layers. When this happens, portions of the spacers or the capping layer encapsulating the gate structures are undesirably etched away. As a result, the gate structure becomes exposed to the contact plug, causing shorts between the contact plugs and the gate structures. Thus, as can be inferred from
FIG. 1A
, securing a sufficient shoulder remaining is critical to preventing inadvertent shorts between adjacent gate structures and contact plugs.
With the prior art gate structures and the method of manufacturing the same, however, it has not been easy to fabricate a self-aligned contact with a sufficient shoulder remaining or etch margin without using complicated and costly process steps. This is especially true today when design rules permit features sizes below 0.18 micrometers (&mgr;m).
The invention disclosed in U.S. Pat. No. 5,989,987 attempts to improve the basic SAC process by chemically etching the silicide layer using a wet etchant that is selective against a silicide to constrict the silicide layer
13
laterally. The resulting structure is shown in FIG.
1
B. However, using the wet etching approach of U.S. Pat. No. 5,989,987 is subject to many process control variables and contamination, requiring a long etching time as well as subsequent cleaning steps.
Accordingly, a need remains for improved SAC technology and gate structures that provide a sufficient shoulder remaining or etch margin but use fewer and simplified process steps.
SUMMARY OF THE INVENTION
The present invention includes a novel gate structure that has an increased etch margin.
Further, the present invention provides an improved method of manufacturing a self-aligned contact with simpler and less costly process steps compared to the conventional contact processing.
In accordance with one aspect of the present invention, a method is provided for fabricating a semiconductor device on a semiconductor substrate. The method includes forming a gate oxide layer on the semiconductor substrate. Then a first conductive layer is formed overlying the gate oxide layer. Next, a second conductive layer, preferably a refractory metal silicide (e.g. WSi
x
), is formed overlying the first conductive layer. A capping layer is formed overlying the second conductive layer. Then the capping layer is etched to form a patterned capping layer having a lower outside corner. An upper portion of the second conductive layer is selectively dry etched laterally to form a lateral recess under the capping layer to increase etch margin. A lower portion of the second conductive layer is etched anisotropically down to the first conductive layer along sidewall approximately vertically aligned with the corner.
In the present invention, a lateral recess for increasing etch margin can be formed in a portion of the second conductive layer while the gate structure is constructed. Preferably, the lateral recess is formed by dry etching, thus avoiding potentially expensive and time-consuming wet etching processes, the latter of which causes more contamination and requires additional process steps. Therefore, the present invention is simple and requires fewer process steps taking shorter process time compared to conventional processes. Manufacturing cost is reduced and yield is increased.


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