Gate technology for strained surface channel and strained...

Details Gate technology for strained surface channel and strained... Gate technology for strained surface channel and strained...

2005-01-25

2005-01-25

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S300000, C438S305000

Reexamination Certificate

active

06846715

ABSTRACT:
A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1−xGexlayer on a substrate, a strained channel layer on the relaxed Si1−xGexlayer, and a Si1−yGeylayer; removing the Si1−yGeylayer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.

REFERENCES:
patent: 5166084 (1992-11-01), Pfiester
patent: 5212110 (1993-05-01), Pfiester et al.
patent: 5981400 (1999-11-01), Lo
patent: 6111267 (2000-08-01), Fischer et al.
patent: 6154475 (2000-11-01), Soref et al.
patent: 6191432 (2001-02-01), Sugiyama et al.
patent: 6207977 (2001-03-01), Augusto
patent: 6218677 (2001-04-01), Broekaert
patent: 6350993 (2002-02-01), Chu et al.
patent: 6407406 (2002-06-01), Tezuka

Affiliated with

Also associated with

Rating

Gate technology for strained surface channel and strained... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Gate technology for strained surface channel and strained..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate technology for strained surface channel and strained... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3392325