Gate structures having sidewall spacers using selective...

Details Gate structures having sidewall spacers using selective... Gate structures having sidewall spacers using selective...

2001-08-10

2004-05-25

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S216000

Reexamination Certificate

active

06740549

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor devices and, more particularly, to a semiconductor device having sidewall spacers and method of manufacturing thereof.
2. Description of the Related Art
SAC (self-aligned contact) technology has been utilized to form self-aligned contact holes between closely spaced gate stacks to accommodate ever-increasing density in ULSI (ultra large scale integration) circuits.
The SAC technology uses a selective etching process to form contact holes. In this technology, as shown in
FIG. 1
, a capping layer
10
and a pre-metal dielectric (PMD) layer
12
are deposited over a gate electrode
14
, thereby forming closely-spaced gate stacks
16
. Nitride sidewall spacers
15
are typically formed along opposite sides of the gate stacks
16
. The selective etch process is designed to remove material from the PMD layer
12
faster than it removes material from the capping layer
10
or the sidewall spacers
15
. Nitrides and oxides are typically used for the capping and PMD layers
10
,
12
, respectively.
However, with this SAC structure, filling the narrow gaps between the gate stacks
16
is very difficult with conventional semiconductor fabrication technologies, especially when the aspect ratio is high as is the case for state-of-the art semiconductor devices. Thus, as shown in
FIG. 1
, undesirable voids
18
can be formed between the gate stacks
16
during the deposition of the PMD layers
12
. This has been a serious problem because adjacent contact holes can be connected through the voids
18
. Thus, shorts between contact fillings (plugs) can occur unintentionally, causing device failures.
Such a problem has been recognized by the semiconductor industry, for example, as disclosed in U.S. Pat. No. 5,789,314, field on Dec. 5, 1995 and issued on Aug. 4, 1998 to Integrated Device Technology, Inc., Santa Clara. Calif. U.S. Pat. No. 5,789,314 discloses suppressing or eliminating void formation during the manufacture of integrated circuits by overlying conductive lines with an oxide layer and removing a portion of the oxide layer to create recesses at regular intervals between the conductive lines. However, such attempt has not been entirely successful as integration density increases as described above.
Accordingly, a need remains for forming gate stack structures having sidewall spacers that enable sufficient gap filling by a dielectric without forming voids therebetween.
SUMMARY OF THE INVENTION
Gate structures with sidewall spacers having improved profiles to suppress or eliminate void formation between the gate structures during gap-filling are disclosed, along with a method of forming the gate structures over a semiconductor substrate.
In accordance with one aspect of the present invention, a gate dielectric layer is formed on a semiconductor substrate. Then, a multi-layer gate stack having a sidewall is formed over the gate dielectric layer. The gate stack comprises a conductive layer and a capping nitride layer overlying the conductive layer. A liner is selectively deposited over the gate stack such that the liner is deposited on the capping nitride layer at a rate lower than the rate of deposition on the conductive layer. Thus, the liner is substantially thinner on the capping nitride layer than on the conductive layer. A sidewall spacer is formed over the liner.
When two gate stacks are spaced closely together, the method of the invention enables filling the intervening gap without forming voids between the gate stacks.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention that proceeds with reference to the accompanying drawings.


REFERENCES:
patent: 4981810 (1991-01-01), Fazan et al.
patent: 5001079 (1991-03-01), Van Laarhoven et al.
patent: 5091763 (1992-02-01), Sanchez
patent: 5208472 (1993-05-01), Su et al.
patent: 5430328 (1995-07-01), Hsue
patent: 5436190 (1995-07-01), Yang et al.
patent: 5518959 (1996-05-01), Jang et al.
patent: 5700580 (1997-12-01), Becker et al.
patent: 5731236 (1998-03-01), Chou et al.
patent: 5789314 (1998-08-01), Yen et al.
patent: 5824588 (1998-10-01), Liu
patent: 5827747 (1998-10-01), Wang et al.
patent: 5827782 (1998-10-01), Shih
patent: 5885890 (1999-03-01), Dennison
patent: 6001719 (1999-12-01), Cho et al.
patent: 6008544 (1999-12-01), Itano
patent: 6025260 (2000-02-01), Lien et al.
patent: 6033981 (2000-03-01), Lee et al.
patent: 6136695 (2000-10-01), Lee et al.
patent: 6140219 (2000-10-01), Dennison
patent: 6156636 (2000-12-01), Yeom et al.
patent: 6165879 (2000-12-01), Lee et al.
patent: 6171954 (2001-01-01), Hsu
patent: 6174802 (2001-01-01), Huang et al.
patent: 6194302 (2001-02-01), Shen
patent: 6207554 (2001-03-01), Xu et al.
patent: 6281084 (2001-08-01), Akatsu et al.
patent: 6335279 (2002-01-01), Jung et al.
patent: 6486506 (2002-11-01), Park et al.
patent: 6566236 (2003-05-01), Syau et al.
Elbel, et al., “A New STI Process Based on Selective Oxide Deposition”;Symposium on VLSI Technology Digest of Technical Papers; pp. 208-209 (1998).

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