Gate/drain capacitance reduction for double gate-oxide DMOS with

Details Gate/drain capacitance reduction for double gate-oxide DMOS with Gate/drain capacitance reduction for double gate-oxide DMOS with

1998-02-11

2000-04-11

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438212, 438232, H01L 218238

Patent

active

060487593

ABSTRACT:
This invention discloses a DMOS power device supported on a substrate of a first conductivity type functioning as a drain. The DMOS power device includes a polysilicon-over-double-gate-oxide gate disposed on the substrate includes a polysilicon layer disposed over a double-gate-oxide structure having a central thick-gate-oxide segment surrounded by a thin-gate-oxide layer with a thickness of about one-fourth to one-half of a thickness of the thick-gate-oxide segment. The DMOS power device further includes a body region of a second conductivity type disposed in the substrate underneath the thin-gate-oxide layer around edges of the central thick-gate-oxide segment the body region extending out laterally to a neighboring device circuit element. The DMOS power device further includes a source region of the first conductivity type disposed in the substrate encompassed in the body region having a portion extending laterally underneath the thin-gate-oxide layer. The DMOS power device further includes an insulation layer covering the polysilicon-over-double-gate-oxide gate with contact openings above the substrate exposing the source region and the body region.

REFERENCES:
patent: 3846822 (1974-11-01), Riley et al.
patent: 5430316 (1995-07-01), Contiero et al.
patent: 5444002 (1995-08-01), Yang
patent: 5563437 (1996-10-01), Davies et al.
patent: 5729037 (1998-03-01), Hshieh et al.
patent: 5741737 (1998-04-01), Kachelmeier
patent: 5814859 (1998-09-01), Ghezzo et al.
patent: 5907169 (1999-05-01), Hshieh et al.

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