Gate trim process using either wet etch or dry etch approach...

Details Gate trim process using either wet etch or dry etch approach... Gate trim process using either wet etch or dry etch approach...

2009-04-15

2011-11-29

Reames, Matthew (Department: 2893)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S707000, C257SE21215

Reexamination Certificate

active

08067314

ABSTRACT:
Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

REFERENCES:
patent: 7687339 (2010-03-01), Schultz et al.
patent: 2008/0233746 (2008-09-01), Huang et al.

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