Gate structure with high K dielectric

Details Gate structure with high K dielectric Gate structure with high K dielectric

2002-11-19

2003-12-16

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S368000, C257S332000

Reexamination Certificate

active

06664160

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a method for manufacturing a gate structure incorporating a high K dielectric therein.
DESCRIPTION OF THE PRIOR ART
As is well known, a semiconductor device has been down-sized by a scale-down of a design rule. Therefore, a gate oxide tends to rapidly approach 30 Å in thickness and below to increase the capacitance between a gate electrode and a channel region. However, the use of silicon dioxide as a gate dielectric is limited at such thicknesses. Once silicon dioxide is formed to a thickness of less than 40 angstroms, direct tunneling may occur through the gate dielectric to the channel region, thereby increasing the leakage current associated with the gate electrode and the channel region, causing an increase in power consumption.
Since reducing the thickness of the gate dielectric inherently increases the gate-to-channel leakage current, alternative methods have been developed to reduce this leakage current while maintaining thin, SiO
2
-equivalent, thickness. One of these methods is to use a high K dielectric material such as Ta
2
O
5
as the gate dielectric material to increase the capacitance between the gate and the channel.
However, if a poly-silicon is utilized as a gate electrode, the use of Ta
2
O
5
for the gate dielectric material has a disadvantage in integrating the semiconductor device. That is, an undesired SiO
2
and TaSi
2
are formed at an interface between Ta
2
O
5
and the poly-silicon which, in turn, increases an equivalent oxide thickness. In order to overcome this problem, a barrier metal such as TiN is employed. However, the TiN changes a threshold voltage shift.
Therefore, there is still a demand for developing a high K dielectric as a gate oxide with excellent leakage current characteristic as well as a low interface state with both a gate electrode and a silicon substrate.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a gate structure incorporating therein a high K dielectric for use in a semiconductor device.
It is another object of the present invention to provide a method for manufacturing a gate structure incorporating therein a high K dielectric for use in a semiconductor device.
In accordance with one aspect of the present invention, there is provided a gate structure for use in a semiconductor device, comprising a semiconductor substrate provided with an isolation region formed therein; a gate dielectric, made of HfO
2
, formed on the semiconductor substrate; and a gate line on the gate dielectric.
In accordance with another aspect of the present invention, there is provided a gate structure for use in a semiconductor device, comprising a semiconductor substrate provided with an isolation region formed therein; a trench structure formed on the semiconductor substrate; a gate dielectric, made of HfO
2
, formed on the trench structure; and a gate line on the gate dielectric.
In accordance with another aspect of the present invention, there is provided a method for manufacturing a gate structure for use in a semiconductor device, the method comprising the steps of a) preparing a semiconductor substrate provided with an isolation region formed therein; b) forming a dummy layer on the semiconductor substrate; c) patterning the dummy layer into a predetermined configuration; d) implanting dopants into the semiconductor substrate by using the patterned dummy layer as a mask, thereby obtaining a source and a drain; e) forming an inter-layer dielectric (ILD) on the semiconductor substrate and the patterned dummy layer; f) planarizing the ILD layer until a top surface of the patterned dummy layer is exposed; g) removing the patterned dummy layer, thereby opening a portion of semiconductor substrate; h) forming a HfO
2
layer on the exposed portion of the semiconductor substrate and the ILD layer; i) forming a conductive layer on the HfO
2
layer; and j) planarizing the conductive layer and the HfO
2
layer until a top surface of the ILD layer is exposed.


REFERENCES:
patent: 6013553 (2000-01-01), Wallace et al.
patent: 6020024 (2000-02-01), Maiti et al.
patent: 6087231 (2000-07-01), Xiang et al.
patent: 6096590 (2000-08-01), Chan et al.
patent: 6200866 (2001-03-01), Ma et al.
patent: 6207589 (2001-03-01), Ma et al.
patent: 6221712 (2001-04-01), Huang et al.
patent: 6320784 (2001-11-01), Muralidhar et al.
patent: 6376888 (2002-04-01), Tsunashima et al.
US patent application Paper US 2001/00533601 A1 By Mogami.

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