Gate technology for strained surface channel and strained...

Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers

Reexamination Certificate

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C438S285000, C438S287000, C257SE21409, C257SE21129

Reexamination Certificate

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11013838

ABSTRACT:
A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGexlayer on a substrate, a strained channel layer on the relaxed Si1-xGexlayer, and a Si1-yGeylayer; removing the Si1-yGeylayer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.

REFERENCES:
patent: 5166084 (1992-11-01), Pfiester
patent: 5212110 (1993-05-01), Pfiester et al.
patent: 5981400 (1999-11-01), Lo
patent: 6074919 (2000-06-01), Gardner et al.
patent: 6096590 (2000-08-01), Chan et al.
patent: 6103559 (2000-08-01), Gardner et al.
patent: 6111267 (2000-08-01), Fischer et al.
patent: 6154475 (2000-11-01), Soref et al.
patent: 6162688 (2000-12-01), Gardner et al.
patent: 6191432 (2001-02-01), Sugiyama et al.
patent: 6194722 (2001-02-01), Fiorini et al.
patent: 6207977 (2001-03-01), Augusto
patent: 6210988 (2001-04-01), Howe et al.
patent: 6218677 (2001-04-01), Broekaert
patent: 6350993 (2002-02-01), Chu et al.
patent: 6407406 (2002-06-01), Tezuka
patent: 2004/0171223 (2004-09-01), Hammond et al.
patent: 2005/0003229 (2005-01-01), Bedell et al.
Abramo A., et al., “Mobility Simulation of a Novel Si/SiGe FET Structure,” IEEE Electron Device Letters, vol. 17, No. 2, pp. 59-61 (1996).
Mizuno, T. et al., “Electron and Hole Mobility Enhancement in Strained-Si MOSFETs on SIGe-on-Insulator Substrates Fabricated by SIMOX Technology,” IEE Electron Device Letters, vol. 21, No. 5, (2000).
O'Neill, A.G., et al., “Deep Submicron CMOS Based on Silicon Germanium Technology,” IEEE Transactions on Electron Devices. vol. 43, No. 6, pp. 911-918 (1996).
Welser, J., et al., “Evidence of Real-Space Hot-Electron Transfer in High Mobility, Strained-Si Multilayer MOSFETs,” IEEE IEDM Tech. Dig., pp. 545-548 (1993).
Welser, J. et al., “NMOS and PMOS Transistors Fabricated in Strained Silicon/Relaxed Silicon-Germanium Structures,” IEEE IEDM Tech. Dig., pp. 1000-1002 (1992).
Armstrong, “Technology for SiGe Heterostructure-Based CMOS Devices,” Ph.D. Thesis, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science (Jun. 30, 1999).
Wolf, Silicon Processing for the VLSI Era vol. 2: Process Integration, Lattice Press, Sunset Beach, CA, pp. 27, 331 (1990).
Comments to Patent Owner's Response,In rereexamination of U.S. Patent No. 6,846,715, Nov. 27, 2006, 15 pages.
Request for Inter Partes Reexamination Pursuant to 35 U.S.C. §§ 301-318 and 37 C.F.R. § 1.913 of U.S. Appl. No. 6,846,715, Jun. 26, 2006.
International Search Report for PCT Application No. PCT/US01/24614, dated Mar. 11, 2002, 3 pages.
Hellberg, P.E., et al. “Oxidation of Silicon-Germanium Alloys. I. An experimental study ” Journal of Applied Physics, vol. 82, No. 11, pp. 5773-5778, Dec. 1, 1997.
Niino, Takeo and Tatsumi, Toru “SiGe Passivation for Si MBE Regrowth” Japanese Journal of Applied Physics, vol. 29, No. 9, pp. L 1702-L 1704, Sep. 1990.
Wu, Y.H. et al., “High-quality Thermal Oxide Grown on high-Temperature-Formed SiGe,” Journal of the Electrochemical Society, vol. 147, No. 5, pp. 1962-1964, 2000.
Notice of Assignment ofInter PartesReexamination Request, Patent No. 6,846,715, Jul. 27, 2006.
Office Action inInter PartesReexamination, Patent No. 6,846,715, Aug. 30, 2006.
Order Granting/Denying Request forInter PartesReexamination, Patent No. 6,846,715, Aug. 30, 2006.

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