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High performance poly-si1−xgex thin film transistor...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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High performance poly-SiGe thin film transistor and a method...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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High performance schottky-barrier-source asymmetric MOSFETs

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High performance self-aligned silicide process for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High performance SiGe:C HBT with phosphorous atomic layer...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High performance stress-enhance MOSFET and method of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions...
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High performance stress-enhance MOSFET and method of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions...
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High performance stress-enhanced MOSFETs using Si:C and SiGe...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High performance sub-micron P-channel transistor with...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reissue Patent

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High performance system-on-chip using post passivation process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High performance three-dimensional TFT-based CMOS inverters,...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High performance transistor with a highly stressed channel

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High performance transistors with hybrid crystal orientations

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High performance varactor diodes

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High performance vertical PNP transistor method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High performance, low power vertical integrated CMOS devices

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High performance/high density BICMOS process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High permittivity silicate gate dielectric

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High permittivity silicate gate dielectric

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High power PMOS device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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