High performance stress-enhance MOSFET and method of...

Details High performance stress-enhance MOSFET and method of... High performance stress-enhance MOSFET and method of...

2006-04-28

2009-10-27

Mandala, Victor (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

C438S938000, C257S213000, C257SE21615

Reexamination Certificate

active

07608489

ABSTRACT:
The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.

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