Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-14
2004-10-12
Lee, Hsien Ming (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S231000, C438S379000, C438S979000
Reexamination Certificate
active
06803269
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates generally to varactor diodes, and more particularly to a varactor diode that has enhanced properties for RF CMOS and BiCMOS applications.
2. Background Art
Variable reactors (varactors) are essential for the design of key radio frequency (RF) CMOS and BiCMOS circuits, and are specifically used as tuning elements in voltage controlled oscillators (VCOs), phase shifters, and frequency multipliers. A varactor is a diode having a capacitance that varies as a function of applied voltage. Examples of such diodes include U.S. Pat. No. 3,396,317, “Surface-Oriented High Frequency Diode;” U.S. Pat. No. 3,634,738, “Diode Having a Voltage Variable Capacitance Characteristic and Method of Making Same;” U.S. Pat. No. 3,636,420, “Low-Capacitance Planar Varactor Diode;” and U.S. Pat. No. 3,860,945, “High Frequency Voltage-Variable Capacitor.”
In order to enhance the capacitive swing of a varactor it also known to vary the dopant concentration of one or both of the diffused electrodes of the diode such that the diffusion has a retrograde dopant profile (that is, the dopant concentration is higher at the lower portion of the diffusion region than it is in the top). These so-called “hyperabrupt” junctions greatly increase the change in varactor capacitance for a given voltage swing. See U.S. Pat. No. 3,638,300, “Forming Impurity Regions In Semiconductors;” U.S. Pat. No. 3,706,128, “Surface Barrier Diode Having a Hypersensitive N Region Forming a Hypersensitive Voltage Variable Capacitor.” U.S. Pat. No. 4,226,648, “Method of Making a Hyperabrupt Varactor Diode Utilizing Molecular Beam Epitaxy;” and U.S. Pat. No. 4,827,319, “Variable Capacity Diode With Hyperabrupt Profile and Plane Structure and the Method of Forming Same.”
In general, varactor designs must maximize a number of properties. One is “tunability,” which is the ratio between the highest and lowest capacitive values (Cmax/Cmin) over the range of applied voltages for the circuit. Another is “linearity.” There are two definitions of ‘linearity’: 1/sqrt(C) and d(InC)/dV, where C is the voltage-dependent varactor capacitance. In the first case it is desired that 1/sqrt(C) be a straight line and the second that d(InC)/dV be a constant, both as V varies. Yet another property is “Q,” or quality factor, which a function of the series resistance of the diode and the capacitive value of the varactor at the higher frequency ranges of the circuit. See Kannnam et al, “Design Considerations of Hyperabrupt Varactor Diodes,” IEEE Transactions of Electron Devices, Vol. ED-18, No. 2, February 1971 pp. 109-115 for a discussion of the interplay between tunability and Q.
In practice, it has proven to be difficult to simultaneously enhance tunability, linearity, and Q of a varactor when Integrated Into a CMOS or BiCMOS process. For example, considering the PFET source/drain junction and well as a varactor device, additional n-well implants will decrease the well resistance and increase varactor Q, but will decrease varactor tuning range by making the source/drain p-n junction depletion regions smaller.
Accordingly, a need has developed in the art for a varactor design that optimizes the tradeoffs between all of these properties, particularly when integrated into a process for forming other integrated circuit devices.
SUMMARY OF THE INVENTION
It is thus an object of the present invention to provide a varactor that optimizes the tradeoffs between tunability, Q, and linearity.
It is another object of the invention to provide a varactor that has maximized tunability, Q, and linearity when integrated into a process for forming other integrated circuit devices.
The foregoing and other objects of the invention are realized, in a first aspect, by a varactor diode comprising a well region of a first conductivity type in a substrate; a plurality of isolation regions on upper portions of the well region; a plurality of masking structures having first and second sides formed on the substrate between respective ones of said plurality of isolation regions; a first plurality of diffusion regions of a second conductivity type, at least some of said plurality of diffusion regions abutting respective ones of said plurality of isolation regions; and a second plurality of diffusion regions of said first conductivity type abutting portions of said first plurality of diffusion regions that do not abut respective ones of said plurality of isolation regions, said second plurality of diffusion regions extending below respective sides of respective ones of said plurality of masking structures, wherein respective ones of said second plurality of diffusion regions do not contact one another.
Another aspect of the invention is a varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions, said varactor having a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, and an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V.
Yet another aspect of the invention is a method of forming a varactor diode in a substrate, comprising forming a well region of a first conductivity type in the substrate; forming a plurality of isolation regions on upper portions of the well region; forming a plurality of masking structures having first and second sides formed on the substrate between respective ones of said plurality of isolation regions; forming a first plurality of diffusion regions of a second conductivity type, at least some of said plurality of diffusion regions abutting respective ones of said plurality of isolation regions; and forming a second plurality of diffusion regions of said first conductivity type abutting portions of said first plurality of diffusion regions that do not abut respective ones of said plurality of isolation regions, said second plurality of diffusion regions extending below respective sides of respective ones of said plurality of masking structures, wherein respective ones of said second plurality of diffusion regions do not contact one another.
A further aspect of the invention is a method of forming an integrated circuit on a semiconductor substrate, comprising forming first and second well regions of a first conductivity type in the substrate; forming a plurality of isolation regions on upper portions of each of said well regions; forming a plurality of conductive structures having first and second sides on each of said well regions, said structures comprising masking structures on said first well regions and gate electrodes on said second well regions; masking said second well regions; forming a first plurality of diffusion regions of a second conductivity type in said first well regions, at least some of said plurality of diffusion regions abutting respective ones of said plurality of isolation regions; and forming a second plurality of diffusion regions of said first conductivity type in said first well regions abutting portions of said first plurality of diffusion regions that do not abut respective ones of said plurality of isolation regions, said second plurality of diffusion regions extending below respective sides of respective ones of said plurality of masking structures, wherein respective ones of said second plurality of diffusion regions do not contact one another.
REFERENCES:
patent: 3396317 (1968-08-01), Vendelin
patent: 3634738 (1972-01-01), Leith et al.
patent: 3636420 (1972-01-01), Vendelin
patent: 3638300 (1972-02-01), Foxhall et al.
patent: 3706128 (1972-12-01), Heer
patent: 3860945 (197
Coolbaugh Douglas D.
Furkay Stephen S.
Hammad Mohamed Youssef
Johnson Jeffrey B.
Canale Anthony J.
Lee Hsien Ming
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