Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reissue Patent
1995-11-30
2001-05-01
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S217000, C438S298000, C438S449000, C438S450000, C438S528000, C438S305000
Reissue Patent
active
RE037158
ABSTRACT:
FIELD OF THE INVENTION
This invention is related to semiconductor devices. Specifically it is related to high-performance sub-micron channel length P-channel MOS (metal-oxide-semiconductor) transistor (PMOS for short) for the Very Large Scale Integrated (VLSI) or the Ultra Large Scale Integrated (ULSI) circuits. It employs the use of Germanium implant into the channel regions of transistors to both pre-amorphize the channel surface to alleviate the channelling of subsequent enhancement implant required by threshold voltage Vt adjustment and to retard the diffusion of the boron dopants (from enhancement implant) in the region to form a very shallow enhancement implant profile.
BACKGROUND OF THE INVENTION
The invention uses various materials which are electrically either conductive, insulating or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a “semiconductor”. One of the materials used is silicon, which is used as either single crystal silicon or as polycrystalline silicon material, referred to as polysilicon or “poly” in this disclosure.
Shallow channel junction will reduce significantly the undesirable short channel effects of transistors. This is significant in the fabrication of sub-micron P-channel (P-CH) transistors in which n+ doped poly gate is used and buried channel is formed. It is desired to further reduce or even solve P-channel buried channel-induced short channel effects and enable further decrease in device length to the sub-micron range.
The prior art relating to Germanium in VLSI devices has been in the area of (1) field isolation improvement and (2) transistor source/drain regions to achieve shallow source and drain junctions. The former deals with device isolation and an improvement in electrical encroachment; yet it does not improve transistor performance; the later deals with device performance by means of achieving shallower source drain junction depths so that the reduction in charge-sharing effect would improve transistor short channel characteristics. It however does not solve or reduce P-channel transistor short channel effects caused by the very nature of buried channel behaviour.
SUMMARY OF THE INVENTION
The present invention deals directly with PMOS buried channel characteristics by making the buried channel enhancement implant profile more shallow. The shallow implant profile results in the P-CH device will have less or no buried channel characteristics. This avoids undesirable short channel effects, and therefore permits further reduction in the transistor channel length.
The shallow profile causes surface channel characteristics to be dominant. Surface channel devices will have better short channel characteristics, i.e., higher punch through voltage BVDSS, less V
T
sensitivity to the drain voltage (defined as curl) and better subthreshold leakage characteristics.
Implantation of germanium into the channel to permit the enhancement implant profile to be made shallower will reduce or event solve P-channel buried channel-induced short channel effects and enable further decrease in device length to deep sub-micron range.
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Ozturk et al., “Optimization of the Germanium Preamorphization Conditions for Shallow-Junction Formation”, IEEE Trans. on Electron Devices, vol. 35, No. 5, May 1988, pp. 659-668.*
Pfiester et al., “Novel Germanium/Boron Channel-Stop Implantation for Submicron CMOS”, IEDM 1987, pp. 740-743.*
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Micro)n Technology, Inc.
Trask, Britt & Rossa
Wilczewski Mary
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