High performance transistor with a highly stressed channel

Details High performance transistor with a highly stressed channel High performance transistor with a highly stressed channel

2008-01-29

2008-01-29

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S218000, C438S294000, C257SE21177

Reexamination Certificate

active

07323392

ABSTRACT:
A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.

REFERENCES:
patent: 6730551 (2004-05-01), Lee et al.
patent: 6881635 (2005-04-01), Chidambarrao et al.
patent: 7238555 (2007-07-01), Orlowski et al.
patent: 2003/0162348 (2003-08-01), Yeo et al.
patent: 2003/0227072 (2003-12-01), Forbes et al.
patent: 2004/0175872 (2004-09-01), Yeo et al.
patent: 2005/0242340 (2005-11-01), Chidambarrao et al.
patent: 2007/0134859 (2007-06-01), Curello et al.
Yin, H., et al., “Fully-Depleted Strained-Si on Insulator NMOSFETs without Relaxed SiGe Buffers,” IEDM, 2003, pp. 53-56.
Yeo, Y.-C., et al., “Enhanced Performance in Sub-100 nm CMOSFETs Using Strained Epitaxial Silicon-Germanium,” IEDM, 2000, pp. 753-756.
Nayak, D. K., et al., “Enhancement-Mode Quantum-Well GexSi1-−PMOS,” IEEE Electron Device Letters, vol. 12, No. 4, Apr. 1991, pp. 154-156.
Ismail, K., et al., “Electron Transport Properties of Si/SiGe Heterostructures: Measurements and Device Implications,” Appl. Phys. Lett., vol. 63, No. 5, Aug. 2, 1993, pp. 660-662.
Kawasaki, H., et al., “Impact of Parasitic Resistance and Silicon Layer Thickness Scaling for Strained-Silicon MOSFETs on Relaxed Si1-−Ge−Virtual Substrate,” IEEE, 2004, 4 pages.

Affiliated with

Also associated with

Rating

High performance transistor with a highly stressed channel does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High performance transistor with a highly stressed channel, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance transistor with a highly stressed channel will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2815046