Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1997-12-23
2002-09-03
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S149000, C438S153000, C438S154000, C438S164000, C438S479000, C438S933000
Reexamination Certificate
active
06444509
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a novel high-performance thin film transistor having an active region and a gate, whose active region comprises a poly-Si
1−x
Ge
x
alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si
1−x
Ge
x
alloy material and the gate and a method for fabricating such a high-performance thin film transistor.
2. Discussion of the Background
Conventional thin-film transistors (TFTs) are commonly employed in high-density static random access memory cells (SRAMs) for load pull-up devices, as well as used both as switching elements and as peripheral driver circuitry in large-area active-matrix liquid crystal displays (LCDs). In such conventional thin film transistors, polycrystalline silicon (poly-Si) is widely used as the active region. Unfortunately, the performance of a poly-Si TFT degrades substantially as the processing temperature decreases. This performance degradation removes many of the incentives to use a poly-Si TFT, because low-temperature processing is necessary in SRAM fabrication to preserve the underlying dopant profiles and to allow for less expensive glass substrates in LCD manufacture.
To overcome these limitations regarding poly-Si TFTs, poly-Si
1−x
Ge
x
materials have been employed in the low temperature manufacture of thin film transistors. Such transistors are described in King,
Applications of Polycrystalline Silicon-Germanium Thin Films in Metal-Oxide-Semiconductor Technologies
, Technical Report No. ICL 94-031 (1994); King et al.,
IEDM
, 91, 567 (1991); and King,
IEEE Electron Device Letters
, 13, 309 (1992). However, in these thin film transistors, while a poly-Si
1−x
Ge
x
material is employed as the active region, a channel layer of silicon is not interposed between the poly-alloy material and the gate. As these investigators themselves noted, the performance of such poly-Si
1−x
Ge
x
TFTs was not superior to that of the poly-Si TFTs. Moreover, experiments performed by the present inventors indicated that the interface trap state density as calculated from the measured subthreshold slope is not improved in a poly-Si
1−x
Ge
x
TFT relative to poly-Si TFT, and, in the case of an NMOS poly-Si
1−x
Ge
x
TFT is significantly diminished.
In an attempt to construct a poly-Si
1−x
Ge
x
TFT whose performance would match or exceed that of poly-Si TFTs, an investigation was undertaken to fabricate a superior poly-Si
1−x
Ge
x
TFT. Hypothesizing that a very-thin-film silicon layer interposed between a poly-Si
1−x
Ge
x
alloy material and a gate, where the silicon layer is thick enough to result in a high quality poly-Si/SiO
2
interface and yet thin enough to allow the channel region to reside at least in part within the poly-Si
1−x
Ge
x
layer, might result in a superior poly-Si
1−x
Ge
x
TFT, a poly-Si
1−x
Ge
x
TFT having an active region and a gate was constructed, whose active region comprises a poly-Si
1−x
Ge
x
alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si
1−x
Ge
x
alloy material and the gate. Such a TFT had not been disclosed in the prior art.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a novel high-performance poly-Si
1−x
Ge
x
thin film transistor.
It is another object of the present invention to provide a method of fabricating a high-performance poly-Si
1−x
Ge
x
thin film transistor.
These objects, among others, have been obtained with a thin film transistor having an active region and a gate, whose active region comprises a poly-Si
1−x
Ge
x
alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si
1−x
Ge
x
alloy material and the gate. Such objects have also been achieved by means of a method of fabricating a poly-Si
1−x
Ge
x
TFT having an active region and a gate, whose active region comprises a poly-Si
1−x
Ge
x
alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si
1−x
Ge
x
alloy material and the gate.
Such poly-Si
1−x
Ge
x
thin film transistors are useful for peripheral logic circuits and pixels in active-matrix liquid crystal displays and for load devices in high density SRAMs.
REFERENCES:
patent: 5019882 (1991-05-01), Solomon et al.
patent: 5241197 (1993-08-01), Murakami et al.
patent: 5250818 (1993-10-01), Saraswat et al.
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 5643826 (1997-07-01), Ohtani et al.
King et al., Polycrystalline Silicon-Germanium TFTs, IEEE TEOD, pp. 1581-1591, Sep. 1994.*
King et al., Low-Temp. (<550 C) Fabrication of Poly-Si TFTs, IEEE EDL, pp. 309-311, Jun. 1992.
Noguchi Takashi
Reif Rafael
Tang Andrew J.
Tsai Julie
Brairton Scott
Kananen, Esq. Ronald P.
Pham Long
Rader & Fishman & Grauer, PLLC
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