High performance vertical PNP transistor method

Details High performance vertical PNP transistor method High performance vertical PNP transistor method

2007-09-04

2007-09-04

Smith, Zandra V. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S203000, C438S969000, C438S417000, C438S322000

Reexamination Certificate

active

10863630

ABSTRACT:
The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow. The resulting structure significantly enhances PNP device performance.

REFERENCES:
patent: 5426316 (1995-06-01), Mohammad
patent: 5837590 (1998-11-01), Latham et al.
patent: 6337252 (2002-01-01), Yoshida
patent: 6759303 (2004-07-01), Cartagena

Affiliated with

Also associated with

Rating

High performance vertical PNP transistor method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High performance vertical PNP transistor method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance vertical PNP transistor method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3771165