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Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Cobalt silicidation process for substrates with a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Code implantation process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Coding method for mask ROM

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Collar dielectric process for reducing a top width of a deep...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Combination of BPTEOS oxide film with CMP and RTA to achieve...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Common gate and salicide word line process for low cost...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Compact self-aligned body contact silicon-on-insulator transisto

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Compact SOI body contact link

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Compact SRAM cell incorporating refractory...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Compact SRAM cell using tunnel diodes

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Compensated-well electrostatic discharge protection devices

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Compensating the workfunction of a metal gate transistor for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Compensation of the channel region critical dimension, after pol

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Compensation technique for parasitic capacitance

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Compensation techniques for substrate heating processes

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Complementary junction-narrowing implants for ultra-shallow...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Complementary metal gate dense interconnect and method of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Complementary metal gates and a process for implementation

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Complementary metal oxide semiconductor (CMOS) gate stack...