Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-07
2003-02-25
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S261000, C438S303000, C438S591000, C438S263000, C438S264000, C438S265000, C438S266000, C438S267000, C438S299000, C438S305000
Reexamination Certificate
active
06524911
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing methods, and more particularly, it relates to a method for manufacturing a non-volatile semiconductor device having a BPTEOS oxide film which is densified and stabilized by RTA followed by CMP so as to achieve good data retention.
2. Description of the Prior Art
In view of the trend in the semiconductor industry for achieving higher and higher packing densities in integrated circuits, multilayer interconnects are being used to connect the electrical components on two different levels. Typically, a BPTEOS layer is used as an interlayer dielectric (ILD) between the two different levels. As is generally known, one of the major concerns in the fabrication of non-volatile memory devices is that of high temperature data retention which is believed to be caused by mobile hydrogen ions. These mobile ions can diffuse to the floating gate in the non-volatile memory devices and cause charge loss.
Traditionally, the prior art semiconductor processing for non-volatile memory devices having BPTEOS oxide films utilized a high temperature heat treatment at equal to or greater than 900° C. for planarization in order to getter mobile ions and thus obtain good data retention. This is sometimes referred to as a “reflow” process. However, the latest metal interconnect technologies involves the use of silicide films, such as a titanium silicide (TiSi
2
) layer or a cobalt silicide (CoSi
2
) layer in the semiconductor manufacturing process. Unfortunately, these silicide films are unable to withstand the high furnace reflow temperatures normally used on the BPTEOS oxide films functioning as the interlayer dielectric for densifying and planarizing the same.
Accordingly, there has arisen a need for a method for manufacturing a non-volatile memory device having a BPTEOS oxide film which eliminates the high temperature reflow process, but yet provides for the densification and planarization of the BPTEOS film. This is achieved in the present invention by utilizing the combination of performing a RTA at the temperature of about 800° C. immediately after the deposition of the BPTEOS film so as to densify and stabilize the same and then performing a CMP step so to planarize the BPTEOS film.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide an improved method for fabricating a non-volatile semiconductor device having a BPTEOS film which overcomes the problems of the prior art methods.
It is an object of the present invention to provide an improved method for fabricating a non-volatile semiconductor device having a BPTEOS film which eliminates the high temperature reflow process, but yet provides for the densification and planarization of the BPTEOS film.
It is another object of the present invention to provide an improved method for fabricating a non-volatile semiconductor device having a BPTEOS film which is densified and stabilized by RTA followed CMP so as to achieve good data retention.
It is still another object to provide an improved method for fabricating a non-volatile semiconductor device having a BPTEOS film which includes the steps of performing a RTA at a temperature of about 800° C. immediately after the deposition of the BPTEOS film so to densify and stabilize the same and then performing a CMP so as to planarize the BPTEOS film.
In accordance with a preferred embodiment of the present invention, there is provided an improved method of fabricating a non-volatile semiconductor device having a BPTEOS oxide film. The present method utilizes the step of performing a RTA at a temperature of about 800° C. immediately after the deposition of the BPTEOS film so as to densify and stabilize the same. Then, a CMP step is performed so as to planarize the BPTEOS film.
REFERENCES:
patent: 4982250 (1991-01-01), Manas, II et al.
patent: 5686336 (1997-11-01), Lee
patent: 6033999 (2000-03-01), Wu et al.
patent: 6284612 (2001-09-01), Wu
Chaudhuri Olik
Lattice Semiconductor Corporation
Nguyen Khiem
LandOfFree
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