Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-04
2002-12-10
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S217000
Reexamination Certificate
active
06492217
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
In the context of insulated gate field effect transistors, the invention relates to integrated circuit devices and more particularly to complementary metal gate devices.
2. Background Information
A metal gate electrode has distinct advantages over a polysilicon gate for current and future technologies of high performance integrated circuit devices. At inversion, a gate electrode of polysilicon, for example, will generally experience a depletion of carriers in the area of the polysilicon near the gate dielectric resulting in a reduced electric field at the surface of the semiconductor. The polysilicon depletion effect is not as significant with gate dielectrics having thicknesses of 50 Å or more. However, as gate dielectric thicknesses decrease, the contribution of the voltage drop at inversion due to the role of the polysilicon depletion effect on device performance will be important. Thus, the polysilicon depletion effect must be accounted for in device scaling. A metal gate electrode does not suffer from the depletion effect associated with a polysilicon gate electrode. A metal gate electrode also reduces the parasitic resistance of a gate electrode line to accommodate the use of longer gate electrodes in integrated circuit design for applications such as stacked gates, word lines, buffer drivers, etc. Longer gate electrodes generally correspond to field effect transistors of greater width.
A semiconductor such as silicon has a certain energy level measured conventionally by its Fermi level. The Fermi level of a material determines its work function. The intrinsic Fermi level of an undoped semiconductor is at the middle of the bandgap between the conduction and valence band edges. In an N-type doped silicon, the Fermi level is closer to the conduction band than to the valence band (e.g., about 4.15 electron-volts). In a P-type doped silicon, the Fermi level is closer to the valence band than the conduction band (e.g., about 5.2 electron-volts).
Metals, metal alloys, metal silicides, metal nitrides, and metal oxides (collectively herein “metals”) have been identified that have work functions similar to the work function of a conventional P-type doped semiconductor substrate and of a conventional N-type doped semiconductor substrate. Examples of metals that have a work function similar to a P-type doped semiconductor material, include but are not limited to, nickel (Ni), Ruthenium oxide (RuO), and molybdenum nitride (MoN). Examples of metals that have a work function similar to an N-type doped semiconductor material, include but are not limited to, ruthenium (Ru), zirconium (Zr), niobium (Nb), tantalum (Ta), titanium silicide (TiSi
2
).
Prior art metal gate electrodes are used in complementary metal oxide semiconductor (CMOS) technology in the form of mid-bandgap (e.g., Fermi level located in the middle of the conduction and valence band of a silicon substrate) metal gate electrodes to maintain the symmetry between NMOS and PMOS devices. The shortcoming of the mid-bandgap metal technique is that a mid-bandgap metal cannot deliver the small threshold voltage (V
T
) necessary for future technologies without degrading short channel effects. To date, however, a complementary metal gate approach with individual work functions optimized for both NMOS and PMOS devices has not been integrated into a workable process. The simple method to deposit complementary metals damages the underlying thin gate dielectrics during patterning, making the transistor with the damaged gate dielectric unusable.
What is needed is a method of utilizing complementary metal gate electrode technology in CMOS circuits.
SUMMARY OF THE INVENTION
A transistor device is disclosed. The transistor device includes a gate dielectric overlying a substrate, a barrier layer overlying the gate dielectric, and a gate electrode overlying the barrier layer. The barrier layer of the device has a physical property that inhibits interaction between the gate dielectric and the gate electrode.
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Bai Gang
Liang Chunlin
Dang Trung
Intel Corporation
Kebede Brook
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