Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-05
2001-03-27
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S655000
Reexamination Certificate
active
06207492
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate both logic and embedded dynamic random access memory, (DRAM), devices, on the same semiconductor substrate, featuring a self-aligned metal silicide, (salicide), layer, formed on the gate structures for both the logic and embedded DRAM devices, while only formed on the source/drain regions of the logic devices.
(2) Description of Prior Art
To decrease the resistance of word lines, for logic devices as well as for DRAM devices, a salicide layer is employed on an underlying polysilicon gate structure. The same salicide layer is also used on the source/drain regions of logic devices, again to increase the conductivity of these elements. However for reliability reasons salicide layers are not used on source/drain regions of DRAM devices. Therefore to reduce cost and process complexity, process sequences have been generated in which both logic and embedded DRAM devices are simultaneously formed on the same semiconductor chip, featuring salicided gate structures and salicided source/drain regions for logic devices, but forming salicide only on the gate structures of the embedded DRAM devices.
Prior art, such as Sung, in U.S. Pat. No. 5,858,831, do show salicide formation on the source/drain regions of logic devices and an absence of salicide on the DRAM source/drain regions. However that prior art does not form a salicide layer on the gate structure, but forms polycide, (metal silicide—polysilicon), gate structures for both logic and DRAM devices, prior to forming a salicide layer on the source/drain region of the logic device. This present invention will describe a process sequence for simultaneous fabrication of both logic devices and embedded DRAM devices, in which salicide layers are simultaneously formed on the gate structures of both device types, but on only the source/drain region of the logic devices, thus presenting the desired performance increase for the logic devices, offered by the salicided source/drain regions, while preventing reliability concerns for the DRAM devices by blocking the salicide formation on the DRAM source/drain regions.
SUMMARY OF THE INVENTION
It is an object of this invention to simultaneously fabricate logic devices and embedded DRAM devices, on the same semiconductor substrate.
It is another object of this invention to simultaneously form a self-aligned metal silicide, (salicide), layer on the gate structures, and on the source/drain regions of the logic devices, and on the gate structures of the DRAM devices, leaving the source/drain regions of the DRAM devices, without salicide.
It is still another object of this invention to use a silicon oxide shape, obtained via a high density plasma, (HDP), deposition, in the spaces between DRAM gate structures, or word lines, to prevent salicide formation on underlying lightly doped source/drain regions.
In accordance with the present invention a process is described for simultaneous fabrication of logic, as well as embedded DRAM devices, on the same semiconductor substrate, featuring the formation of a salicide layer on the gate structures, and source/drain regions of the logic devices, while only forming the same salicide layer only on the gate structures of the DRAM devices. Polysilicon gate, or word line structures are formed on an underlying gate insulator layer, in a first region of the semiconductor substrate, to be used for logic devices, and in a second region of the semiconductor substrate, to be used for the embedded DRAM devices. The embedded DRAM device region is designed with narrow spaces between word lines structures, while the logic device region is designed to accommodate wide, as well as narrow spaces between the word line structures. After formation of lightly doped source/drain, (LDD), regions, in the spaces between gate structures, in both logic and DRAM device regions, silicon nitride spacers are formed on the sides of all gate structures. An HDP silicon oxide layer is next deposited resulting in thick silicon oxide shapes, in the narrow spaces between gate structures, and resulting in thin silicon oxide shapes, located in the wide spaces between gate structures, or word lines. Thin silicon oxide shapes are also formed on the top surface of all gate structures. A dry etch procedure is then used to completely remove the thin silicon oxide shapes from the top surface of all gate structures, as well to remove the thin silicon oxide shapes, located in the wide spaces between gate structures. The same dry etch procedure only removes a portion of the thick silicon oxide shapes located in the narrow spaces between gate structures, resulting in silicon oxide blocking shapes. A photoresist shape is next used as an etch mask to protect the silicon oxide blocking shapes, located in the embedded DRAM device region, while remaining silicon oxide blocking shapes are removed from the wide spaces, located between logic device, gate structures. Heavily doped source/drain regions are next formed in the logic device region, in the spaces between word line or gate structures, while the silicon oxide blocking shapes, prevent formation of the heavily doped source/drain regions, in the embedded DRAM device region. A metal layer is then deposited, followed by an anneal procedure, forming self-aligned metal silicide, (salicide), shapes, on regions in which the metal layer overlayed the top surface of all gate structures, and overlayed the top surface of the heavily doped source/drain region, in the logic device region. Regions of unreacted metal, located on the silicon oxide blocking shapes, as well as on the silicon nitride spacers, are then selectively removed.
REFERENCES:
patent: 5858831 (1999-01-01), Sung
patent: 5897348 (1999-04-01), Wu
patent: 5950090 (1999-09-01), Chen et al.
patent: 5998247 (1999-12-01), Wu
patent: 5998251 (1999-12-01), Wu et al.
patent: 6153459 (2000-11-01), Sun
Chiang Kevin
Tzeng Kuo-Chyuan
Wang Chen-Jong
Ying Tse-Liang
Ackerman Stephen B.
Chaudhari Chandra
Saile George O.
Taiwan Semiconductor Manufacturing Company
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