Compact SRAM cell using tunnel diodes

Details Compact SRAM cell using tunnel diodes Compact SRAM cell using tunnel diodes

1998-11-18

2001-11-13

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S153000, C438S199000, C438S215000, C438S167000

Reexamination Certificate

active

06316305

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of integrated circuit fabrication, and more specifically to a structure for static random access memory cells with tunnel diodes and a method for making the same.
2. Description of the Related Art
The traditional SRAM cell consists of six transistors configured as cross-coupled inverters to form a flip-flop. The minimum attainable cell size has remained at approximately 120 F
2
(where F denotes the feature size—the minimum line width and/or minimum space between lines) using standard planar technology. The drive to achieve further reductions in cell size has led to the use of vertical transistors, but even with this technology, which is more complicated and hence more costly, the feature size cannot be reduced to below 32 F
2
. Thus, although absolute SRAM cell size can be improved with reductions in feature size corresponding to advances in lithography technology, further reductions in SRAM cell size require changes in cell configuration. As used herein, cell configuration refers to the components (e.g. transistors, diodes) of the cell and their interconnection. Configuration has a different meaning from structure. Structure, as used herein, refers to the physical topography of the fabricated cell.
Several different SRAM cell configurations have been proposed. Some of these new structures exploit latchup as a mechanism of cell operation. Other new SRAM cell configurations make use of bipolar base current reversal. Examples of such configurations can be found in Koji Sakui et al.,
A New Static Memory Cell Based on Reverse Base Current
(
RBC
)
Effect of Bipolar Transistors,
1988 IEDM Digest of Technical Papers, pp. 44-47, and in U.S. Pat. No. 5,594,683. These and other new SRAM cell configurations do achieve smaller cell size.
Each of these alternative configurations, however, suffers from an important drawback—high standby power consumption. Standby power consumption is the amount of power used by a cell when neither read nor write accesses are occurring. This drawback is especially problematic in situations such as BBRAM (battery backed-up RAM) where low standby power consumption is crucial.
Another alternative configuration is disclosed in van der Wagt et al.,
RTD/HFET Low Standby Power SRAM Gain Cell
, IEEE Electron Device Letters, vol. 19, No. 1 (January, 1988). This configuration uses only two tunnel diodes and a single FET, but still suffers from relatively high standby power consumption (approximately 50 nanowatts per cell). The high standby power consumption is partially due to the fact that the cell described in van der Wagt is fabricated using III-V technology (integrated circuits fabricated on substrates such as GaAs comprising combinations of elements from groups III and V of the periodic table).
A circuit diagram of this SRAM cell
10
is shown in FIG.
1
. Two tunnel diodes
14
,
16
are connected in series between a voltage source
12
and ground such that the diodes
14
,
16
are both forward biased. The storage node
15
between the diodes
14
,
16
is connected to the drain
18
a
of a field effect transistor
18
. The source
18
b
of transistor
18
is connected to the bit line
20
, while the gate
18
c
of transistor
18
is connected to the word line
22
. In this configuration, the transistor
18
allows access to the storage node
15
much as a transistor controls access to a storage capacitor in a conventional DRAM cell.
FIG. 2
is a plot of the current vs. voltage characteristic curve
40
of the tunnel diodes
14
,
16
. The vertical axis
42
is in milliamps, while the horizontal axis
44
is in volts. The curve
40
exhibits a relative minimum, or valley, current at approximately 0.3 volts (point A in FIG.
2
). As can be seen from line
46
, this same current also occurs at a forward bias of approximately 0.02 volts (point B in FIG.
2
). Thus, a combination of two diodes
14
,
16
forward biased in series with a total bias of 0.32 volts will have a current equal to the valley current indicated by line
46
, with 0.3 volts across one diode and 0.02 volts across the other. Since either diode can have either voltage, two stable states for the diode
14
,
16
combination exist. The node
15
thus acts as the storage node, which can remain stable at either 0.3 or 0.02 volts. The stability of the cell states is determined by the value of the voltage across the diode pair
14
,
16
as illustrated in FIG.
3
. The node
15
can be set to either of these states by applying the desired voltage to the bit line
20
and raising the word line
22
voltage to turn on the access transistor
18
. Reading may be accomplished as in a DRAM cell by using voltage sense amplifier to sense the voltage on the bit line
20
after raising the word line
22
voltage to connect the node
15
to the bit line
20
. Because the node
15
is in a self-sustaining stable voltage state, current sensing may also be used to read the cell state.
What is needed is a compact cell structure and corresponding fabrication method that realizes the above-discussed SRAM circuit configuration in a small amount of space while improving standby mode power consumption.
SUMMARY OF THE INVENTION
The present invention provides a compact structure for the above-discussed SRAM cell as well as a method for fabricating the structure. The structure is implemented in silicon (rather than III-V) technology which results in a reduced standby power consumption of only approximately 0.5 nanowatts. The cell structure realizes an SRAM cell with only a 16 F
2
area using planar technology. The structure of the cell according to one embodiment of the present invention is comprised of first and second voltage bus bars of approximately minimum feature size width, each of which has a tunnel diode formed therein, and an elongated center land area (also of minimum feature size width) between the two bus bars. The transistor is constructed along the elongated center land area. In a preferred embodiment, transistors of neighboring cells share a common drain area and bit line contact. A corresponding method for fabricating the structure is also disclosed.


REFERENCES:
patent: 5032891 (1991-07-01), Takagi et al.
patent: 5594683 (1997-01-01), Chen et al.
patent: 5976926 (1999-11-01), Wu et al.
Jack Y-C. Sun, 1997 International Symposium on VLSIT Technology, Systems and Applications, Digest of Technical Papers, pp. 293-297.
S.D. Malaviya, Single Device DC Stable Memory Cell, IBM Technical Disclosure Bulletin, U20U, No. 9, Feb. 1978.
Koji Sakui et. al. A New Static Memory Cell Based on Reverse Base Current (RBC) Effect of IBipolar Transistors, 1988 IEDM, IDigest of Technical Papers, pp. 44-47.
D. Chin and H. matino, IBM Technical Disclosure Bulletin, 28, No. 12, May 1986, pp. 5522, 5523, Static RAM Cell Configuration.
J.P.A. van der Wagt et. al. IEEE Electron Device Letters, 19, No. 1. Jan. 1998, pp. 7-9, RTD/HFET Low Standby Power SRAM GAin Cell.
R.A. Logan et. al. Journal of Applied Phyusics, 32, No. 7, Jul. 1961, pp. 1201-1206, Electron Bombardment Damage in Silicon Esaki Diodes.

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