Cobalt salicidation method on a silicon germanium film

Details Cobalt salicidation method on a silicon germanium film Cobalt salicidation method on a silicon germanium film

1999-12-30

2001-04-10

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000, C438S294000, C438S589000, C438S595000, C438S604000

Reexamination Certificate

active

06214679

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and more specifically to a cobalt silicide film on a silicon germanium alloy.
2. Discussion of Related Art
Today literally millions of individual transistors are coupled together to form very large-scale integrated (VSLI) circuits, such as microprocessors, memories, and application specific integrated circuits (IC's). Presently, the most advanced IC's are made up of approximately three million transistors, such as metal oxide semiconductor (MOS) field effect transistors having gate lengths on the order of 0.25 &mgr;m. In order to continue to increase the complexity and computational power of future integrated circuits, more transistors must be packed into a single IC (i.e., transistor density must increase). Thus, future ultra large-scale integrated (ULSI) circuits will require very short channel transistors with effective gate lengths less than 0.1 &mgr;m. Unfortunately, the structure and method of fabrication of conventional MOS transistors cannot be simply “scaled down” to produce smaller transistors for higher density integration.
The structure of a conventional MOS transistor
100
is shown in FIG.
1
. Transistor
100
comprises a gate electrode
102
, typically polysilicon, formed on a gate dielectric layer
104
which in turn is formed on a silicon substrate
106
. A pair of source/drain extensions or tip regions
110
are formed in the top surface of substrate
106
in alignment with outside edges of gate electrode
102
. Tip regions
110
are typically formed by well-known ion implantation techniques and extend beneath gate electrode
102
. Formed adjacent to opposite sides of the gate electrode,
102
and over tip regions
110
are a pair of sidewall spacers
108
. A pair of source/drain contact regions
120
are then formed, by ion implantation, in substrate
106
substantially in alignment with the outside edges of sidewall spacers
108
.
As device features are continually scaled down, the source/drain contact resistance negatively impacts device performance. It has been proposed to deposit silicon germanium alloys
122
on the source/drain contract regions
120
to form raised source/drain regions which help reduce the source/drain contact resistance. Generally a low resistance silicide is formed by a self-aligned process, known as a salcide process, on the source/drain regions. Unfortunately, however, present techniques are unable to form a low resistance cobalt silicide film on silicon germanium alloys.
SUMMARY OF THE INVENTION
A method of forming a cobalt germanosilicide film is described. According to the present invention a silicon germanium alloy is formed on a substrate. A cobalt film is then formed on the silicon germanium alloy. The substrate is then heated to a temperature of greater than 850° C. for a period of time less than 20 seconds to form a cobalt germanosilicide film.


REFERENCES:
patent: 5624869 (1997-04-01), Agnello et al.
patent: 5883003 (1999-03-01), Matsubara
patent: 6037922 (2000-03-01), Yagyu

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