Reduced cap layer erosion for borderless contacts

Reduced cell-to-cell shorting for memory arrays

Reduced cell-to-cell shorting for memory arrays

Reduced channel length for a high performance CMOS transistor

Reduced channel length lightly doped drain transistor using a su

Reduced contact area of sidewall conductor

Reduced degradation of metal oxide ceramic due to diffusion...

Reduced dielectric constant spacer materials integration for...

Reduced dopant deactivation of source/drain extensions using...

Reduced hydrogen sidewall spacer oxide

Reduced mask CMOS salicided process

Reduced mask count process for manufacture of mosgated device

Reduced mask process for manufacture of MOS gated devices using

Reduced masking step CMOS transistor formation using...

Reduced parasitic leakage in semiconductor devices

Reduced topography DRAM cell fabricated using a modified...

Reducing agent for high-K gate dielectric parasitic...

Reducing contamination in a process flow of forming a...

Reducing external resistance of a multi-gate device using...

Reducing gate CD bias in CMOS processing