Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-09-30
1999-11-09
Chaudhuri, Olik
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438242, 438243, 438526, H01L 218242
Patent
active
059813326
ABSTRACT:
A trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET. This enables the use of a thinner collar while still achieving a leakage that is acceptable. In one embodiment, the diffusion region is self-aligned.
REFERENCES:
patent: 5185284 (1993-02-01), Motonami
patent: 5234856 (1993-08-01), Gonzalez
patent: 5334547 (1994-08-01), Nakamura
patent: 5543348 (1996-08-01), Hammerl et al.
patent: 5741738 (1998-04-01), Mandelman et al.
L. Nesbit et al., A 0.6 micron 2 256Mb Trench DRAM Cell with Self-Aligned BuriEd STap (BEST), IEDM 93-627, 1993.
S. Wolf et al., Silicon Processing for the VLSI Era, vol. 1, Lattice Press, p. 541, 1986.
S. Wolf, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, pp. 18, 19, 301, 331, 333, and 661, 1990.
K. Ng, Complete Guide to Semiconductor Devices, McGraw-Hill, Inc., pp. 4, 164, and 165, 1995.
Alsmeier Johann
Hsu Louis L. C.
Mandelman Jack A.
Tonti William R.
Braden Stanton C.
Chaudhuri Olik
International Business Machines - Corporation
Mao Daniel H.
Siemens Aktiengesellschaft
LandOfFree
Reduced parasitic leakage in semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reduced parasitic leakage in semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced parasitic leakage in semiconductor devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1455051