Reducing gate CD bias in CMOS processing

Details Reducing gate CD bias in CMOS processing Reducing gate CD bias in CMOS processing

2011-03-22

2011-03-22

Picardat, Kevin M (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S229000, C438S587000

Reexamination Certificate

active

07910422

ABSTRACT:
A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.

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