Reduced masking step CMOS transistor formation using...

Details Reduced masking step CMOS transistor formation using... Reduced masking step CMOS transistor formation using...

2000-08-17

2002-11-12

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S231000, C438S305000

Reexamination Certificate

active

06479350

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing semiconductor devices, i.e., CMOS-type transistor devices and integrated circuits comprising such devices, with improved processing methodology resulting in increased reliability and quality, increased manufacturing throughput, and reduced fabrication cost. The present invention has particular applicability in fabricating high-density integration semiconductor devices with design features below about 0.18 &mgr;m, e.g., about 0.15 &mgr;m.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra-large-scale integration (ULSI) semiconductor devices require design features of 0.18 &mgr;m and below, such as 0.15 &mgr;m and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 &mgr;m and below challenges the limitations of conventional semiconductor manufacturing techniques.
As feature sizes of MOS and CMOS devices have decreased to the sub-micron range, so called “short channel” effects have arisen which tend to limit device performance. For n-channel MOS transistors, the major limitation encountered is caused by hot-electron-induced instabilities. This problem occurs due to high electrical fields between the source and drain, particularly near the drain, such that charge carriers, either electrons or holes, are injected into the gate or semiconductor substrate. Injection of hot carriers into the gate can cause gate oxide charging and threshold voltage instabilities which accumulate over time and greatly degrade device performance. In order to counter and thus reduce such instabilities, lightly-doped source/drain extension-type transistor structures have been developed, as describe below.
For p-channel MOS transistors of shortchannel type, the major limitation on performance arises from “punch-through” effects which occur with relatively deep junctions. In such instances, there is a wider subsurface depletion effect and it is easier for the field lines to go from the drain to the source, resulting in the above-mentioned “punch-through” current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming p-channel MOS transistors.
The most satisfactory solution to date of hot carrier instability problems of MOS and CMOS devices is the provision of lightly- or moderately-doped source/drain extensions driven just under the gate region, while the heavily-doped source/drain regions are laterally displaced away from the gate by use of at least one sidewall spacer on the gate. Such structures are particularly advantageous because they do not have problems with large lateral diffusion and the channel length can be set precisely.
Several processing sequences or schemes have been developed for the manufacture of lightly- or-moderately-doped source/drain extension-type MOS and CMOS transistors for use in high-density integration applications, with a primary goal of simplifying the manufacturing process by reducing and/or minimizing the requisite number of processing steps. Conventional processing schemes for making such MOS and CMOS transistors generally employ disposable sidewall spacers formed on opposing side surfaces of a thin gate insulator/gate electrode layer stack, which sidewall spacers form part of a mask during ion implantation processing for forming laterally-displaced, heavily-doped source/drain regions in the semiconductor substrate on opposite sides of the layer stack.
According to one conventional process scheme employing disposable (i.e., removable) sidewall spacers for making MOS transistors, a precursor structure is provided comprising a semiconductor substrate of one conductivity type and having a layer stack as described above formed on a portion of the substrate surface is subjected to blanket-type dielectric layer deposition and patterning (as by anisotropic etching) to form a sidewall spacer on opposing side surfaces of the layer stack. Opposite conductivity type r or n-type dopant impurities are then implanted into the substrate using the layer stack with sidewall spacers formed thereon as an implantation mask, to thereby form moderately- to heavily-doped implants. High temperature annealing is then performed to thermally activate and diffuse the implanted dopant and reduce lattice damage due to implantation, thereby forming source/drain regions and associated junctions at a predetermined dopant density and depth below the substrate surface. The effective length of the channel of such transistors is determined by the width of the gate insulator/gate electrode layer stack and the width of the sidewall spacers formed thereon. After activation annealing, the sidewall spacers are removed, as by etching, and a second implantation process for implanting n- or p-type opposite conductivity type dopant impurities into the substrate is performed using only the gate insulating layer/gate electrode layer stack as an implantation mask, thereby forming shallow-depth, lightly- or moderately-doped source/drain regions. Following this implantation, a second activation process, e.g., rapid thermal annealing (RTA), is performed for effecting dopant diffusion/activation and relaxation of implantation-induced lattice damage of the implants, to form shallow-depth, lightly- or moderately-doped source/drain extensions extending from respective proximal edges of the heavily-doped source/drain regions to just below the respective proximal edges of the gate insulator/gate electrode layer stack.
In a variant of the above-described process, the sidewall spacers are comprised of a relatively narrow layer of a first (or inner) dielectric material and a relatively wide layer of a second (or outer) dielectric material. According to the process methodology of this variant, only the second, or relatively wide, outer dielectric sidewall spacer layer is removed subsequent to annealing for forming the moderately to heavily-doped source/drain regions. The first, or relatively thin, inner dielectric sidewall spacer layer is retained throughout subsequent processing for protecting the gate insulator layer/gate electrode layer stack, eg., during contact formation.
A conventional approach employing processing methodology such as described above, for forming MOS transistors of different channel conductivity type in or on a common substrate, e.g., CMOS devices, is illustrated in FIGS
1
(A)-
1
(G). As shown in FIG.
1
(A), field oxide areas
115
(or other conventional isolation means, e.g., shallow trench isolation (STI)) are formed, as by local oxidation of silicon (LOCOS), in semiconductor substrate
100
, typically of monocrystalline silicon, to electrically separate p-type regions
101
and n-type regions
102
formed therein, as by conventional dopant diffusion or implantation. A layer stack comprising a thin gate oxide layer
105
formed in contact with substrate
100
, as by thermal oxidation, and an overlying conductive gate electrode layer
100
, such as heavily-doped polysilicon, is formed over a portion of the surface area of each of the oppositely doped regions
101
and
102
. Referring to FIG.
1
(B), a first patterned photoresist mask M
1
is then formed over n-type region
102
and its associated layer stack
105
/
110
and p-type region
101
is implanted, as by ion implantation, with n-type dopant impurities NLDD to form lightly- or moderately-doped regions
120
, termed “shallow source/drain extensions”. Adverting to FIG.
1
(C), first mask M
1
is then removed, and p-type region
101
implanted with n-type impurities and associated layer stack
105
/
110
are masked with second patterned photoresist mask M
2
. N-type region
102
is thereafter implanted, as by ion implantation, with p-type dopant impurities PLDD to form lightly- or moderately-doped shallow source/drain extensions
125
.
Next, as shown in FIG.
1
(D), sidewall spacers
130
are formed on opposing side surfaces of each of the

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