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Memory array with surrounding gate access transistors and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory array with ultra-thin etched pillar surround gate...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell and method for fabricating it

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell and method for fabricating same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell and method for forming the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell and method for forming the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell and method for producing the memory cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell and method of making the memory cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell arrangement and method for its fabrication

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell array in a dynamic random access memory and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell array with a self-aligned, buried bit line

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell arrays and methods for producing memory cell arrays

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell configuration and corresponding fabrication method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell configuration and fabrication method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell fabrication employing an interpoly gate dielectric a

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell fabrication method and memory cell configuration

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell for dynamic random access memory (DRAM)

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell for EEPROM devices, and corresponding fabricating pr

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell for EEPROM devices, and corresponding...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell having an ONO film with an ONO sidewall and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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