Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-08
2002-08-13
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S265000, C438S591000, C438S593000
Reexamination Certificate
active
06432773
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to memory cells of semiconductor devices, and more particularly to a merged two transistor memory cell having an ONO stack film with an ONO sidewall that is placed between a floating gate of the memory transistor and the gate shared between the memory transistor and select transistor and a method of making same.
BACKGROUND OF THE INVENTION
EEPROM (Electrically Erasable Programmable Read Only Memory) cells are a class of nonvolatile semiconductor memory in which information may be electrically programmed into and erased from each memory element or cell. Floating gate EEPROM cells are one type of EEPROM cell in which information is stored by placing electronic charge on a “floating gate”, typically a region of conductive polysilicon that is electrically isolated from other conducting regions of the device by insulating dielectric layers that surround it. The charge on the floating gate can be detected in reading the memory cell because it changes the threshold voltage of the memory transistor. This change in threshold voltage changes the amount of current that flows through the cell when voltages are applied to it during the read operation and the current can be detected by a sense amplifier circuit.
As stated above, EEPROM cells are nonvolatile, which means that they must retain their information (charge state) even when the power supplied to them is turned off. Thus, it is critically important that the charge stored on the floating gate not “leak” off over time. A product containing EEPROM cells usually has a retention specification in its data sheets which states how long the EEPROM memory cells will retain the information programmed into them without error when the power supplied to them is turned off. Retention specifications typically range between 1 and 20 years. Thus, the dielectric isolation surrounding the floating gate must have very good integrity and this integrity must exist with respect to all of the cells in the memory device. Prior art solutions to this problem proved inadequate as the demand for smaller cell size increased.
In one prior art solution, the control gate is isolated from the floating gate by growing a poly-oxide layer, e.g., a silicon dioxide (SiO
2
) layer, on the polysilicon floating gate. The control gate polysilicon layer is then deposited on top of the poly-oxide layer. Silicon dioxide grown on heavily doped polysilicon, however, is not a good quality dielectric, and thus for good charge retention, the polysilicon oxide must be relatively thick (>500A) for a viable manufacturing process. To scale the cell area down, while maintaining the same coupling ratio, and thus the same programming voltages, the oxide between the floating gate and control gate must be thinned down, which in turn jeopardizes the integrity of the charge retention, and thus makes this solution less than desirable for smaller cell size devices.
Later solutions were developed in which a 3-layer stack of dielectrics (ONO), consisting of a bottom layer of silicon dioxide, a middle layer of silicon nitride (Si
3
N
4
), and top layer of silicon dioxide, was used as the dielectric isolation between the floating and control gates. In one later solution, the oxide layers in the ONO stack are either thermally grown on the polysilicon floating gate and silicon nitride layer or deposited films. In this solution, the poly
1
layer forming the floating gate and the ONO stack are etched together, so that the ONO stack is self aligned with the floating gate. After this step, a thermal poly-oxide is formed on the sidewall of the floating gate. A drawback of this solution is that the poly-oxide formed on the sidewall of the floating gate was either too thin or prevent the leakage of charge or too thick to make scalability practical. In another later solution, the poly
1
layer forming the floating gate is etched before the ONO film is formed on the floating gate. The drawback of this solution is that the ONO film forms in the gate area of the select transistor. The reason that it is not desirable to have the ONO film in the gate area of the select transistor is that the silicon nitride layer has a tendency to trap electrons and this causes the threshold voltage of the select transistor to drift with the electrical stress to which it is subject during the program and erase operations. This threshold voltage instability is very damaging to the overall cell reliability.
Both of these later solutions employing an ONO stack film, however, proved to be superior to a purely thermally grown polysilicon oxide or a deposited and annealed oxide alone, with respect to both scalability and charge retention. Another advantage of an all-deposited ONO stack is that the pin hole defect density of the stack is greatly reduced since the probability of pin holes overlapping in all three layers is extremely small. Currently, ONO stacks with effective oxide thickness as low as 200A are used.
The idea of employing an ONO stack to isolate the floating and control gates in a modern EEPROM process has also been applied to a type of floating gate EEPROM cell design known as a “split-gate” cell. In traditional two-transistor byte selectable EEPROM cells, a select transistor
1
is in series with each memory cell transistor
2
, which includes a poly
1
floating gate
3
, as shown in
FIGS. 1 and 2
. In this configuration, the select transistor
1
is used to isolate the memory transistor
2
during the read and erase operations, and each transistor has its own poly
2
gate
4
. The two-transistor configuration takes up considerable area, however. To reduce the die area consumed, it is possible in some cells to merge the select and memory transistors so that they share the same polysilicon gate
30
, as shown in
FIGS. 3 and 4
. (It should be noted that the same reference numerals used in identifying specific elements in
FIGS. 7 and 8
discussed in the detailed description below are used in reference to identical elements referred to in prior art FIGS.
3
-
6
). This same configuration is used to increase the programming efficiency of channel hot carrier programmed EEPROM cells and are known as source-side injection (SSI) cells.
In p-channel EEPROM cells programmed by Fowler-Nordheim tunneling, the shared polysilicon gate
30
′ may completely overlap the floating gate
28
on both sides, thus splitting the select transistor channel on either side of the floating gate memory transistor channel, as shown in
FIGS. 5 and 6
. In either case (
FIG. 3 and 4
or FIGS.
5
and
6
), it is preferable to have an ONO stack separate the floating gate and control gate polysilicon layers (not shown in FIG.
3
-
6
), while at the same time not having the ONO for the gate dielectric of the merged select transistor. Electron trapping still occurs in the ONO stack between the floating and control gates, but this appears as a transient threshold voltage shift of the memory transistor after program or erase and is small in a properly designed process. The threshold shift in the select gate has a more severe effect because the select gate threshold needs to be large enough that bitline current is shut off in a deselected cell, which is in the conductive state. Current leakage in the many deselected cells, which share a common bitline, can cause an “off” cell being read in the one selected wordline to erroneously appear to be in the “on” state.
While the prior solutions employing the ONO stack films are an improvement over earlier solutions employing a thermally grown silicon dioxide layer, they still have several drawbacks. Accordingly, an improved dielectric isolation between the floating gate and control gate is desired.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a memory cell of a semiconductor device is provided. The memory cell includes a first conductive layer having a top surface and a side surface. In one embodiment, the first conductive layer is floating gate of a memory transistor of the memory cell. The memory cell further includes
Deutscher Neil
Gerber Donald S.
Ma Robert P.
Baker & Botts L.L.P.
Microchip Technology Incorporated
Novacek Christy
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