Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-08-18
2004-09-28
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S413000
Reexamination Certificate
active
06797573
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to memory circuits, and more particularly, to dynamic random access memory cells and a method for forming the same.
BACKGROUND OF THE INVENTION
Random access memory (“RAM”) cell densities have increased dramatically with each generation of new designs and have served as one of the principal technology drivers for ultra large scale integration (“ULSI”) in integrated circuit (“IC”) manufacturing. However, in order to accommodate continuing consumer demand for integrated circuits that perform the same or additional functions and yet have a reduced size as compared with available circuits, circuit designers continually search for ways to reduce the size of the memory arrays within these circuits without sacrificing array performance.
With respect to memory ICs, the area required for each memory cell in a memory array partially determines the capacity of a memory IC. This area is a function of the number of elements in each memory cell and the size of each of the elements. For example,
FIG. 1
illustrates an array
100
of memory cells
110
for a conventional dynamic random access memory (DRAM) device. Memory cells
110
such as these are typically formed in adjacent pairs, where each pair is formed in a common active region
120
and share a common source/drain region that is connected to a respective digit line via a digit line contact
124
. The area of the memory cells
110
are said to be 8F
2
, where F represents a minimum feature size for photolithographically-defined features. For conventional 8F
2
memory cells, the dimension of the cell area is 2F×4F. The dimensions of a conventional 8F
2
memory cell are measured along a first axis from the center of a shared digit line contact
124
(½F), across a word line
128
that represents an access transistor (1F), a storage capacitor
132
(1F), an adjacent word line
136
(1F), and half of an isolation region
140
(½F) separating the active region
120
of an adjacent pair of memory cells (i e., resulting in a total of 4F). The dimensions along a second perpendicular axis are half of an isolation region
150
on one side of the active region
120
(½F), the digit line contact
124
(1F), and half of another isolation region
154
on the other side of the active region
120
(½F) (i.e., resulting in a total of 2F).
In some state-of-the-art memory devices, the memory cells for megabit DRAM have cell areas approaching 6F
2
. Although this is approximately a 25% improvement in memory cell area relative to conventional 8F
2
memory cells, as previously described, a further reduction in memory cell size is still desirable. Therefore, there is a need for a compact memory cell structure and method for forming the same.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor memory cell structure. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post formed on the surface of the substrate over the active region. The epitaxial post has at least one surface extending outwardly from the surface of the substrate and another surface opposite of the surface of the substrate. A vertical transistor is formed in the epitaxial post having a gate structure that is formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post. The memory cell further includes a memory cell capacitor formed on an exposed surface of the epitaxial post.
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Dang Phuc T.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
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