Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-01-12
2008-12-09
Huynh, Andy (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S591000, C438S593000, C257S324000, C257SE29309
Reexamination Certificate
active
07462533
ABSTRACT:
A method for fabricating a memory cell includes forming a stacked insulating layer, and a lower conductive layer on a semiconductor substrate, patterning the lower conductive layer and the insulating layer to form a gap region, forming a gate insulating layer on exposed surfaces of the semiconductor substrate and the lower conductive layer in the gap region, forming a gate pattern on the gate insulating layer for filling the gap region, the gate pattern protruded upward to have sidewall portions exposed above the lower conductive layer, forming an upper sidewall pattern on each exposed sidewall portion of the gate pattern, patterning the lower conductive layer and the insulating layer to form a lower sidewall pattern and a charge storage layer under each upper sidewall pattern, wherein the gate pattern and each upper sidewall pattern are used as an etching mask.
REFERENCES:
patent: 6011725 (2000-01-01), Eitan
patent: 6218695 (2001-04-01), Nachumovsky
patent: 6348711 (2002-02-01), Eitan
patent: 6673677 (2004-01-01), Hofmann et al.
patent: 6784476 (2004-08-01), Kim et al.
Jeon Hee-Seog
Kim Jae-Hwang
F. Chau & Associates LLC
Huynh Andy
Samsung Electronics Co,. Ltd.
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