Memory cell fabrication method and memory cell configuration

Details Memory cell fabrication method and memory cell configuration Memory cell fabrication method and memory cell configuration

2002-03-08

2003-09-30

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S594000

Reexamination Certificate

active

06627498

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for the fabrication of a memory cell of an EEPROM and to a construction of such a memory cell.
One of the most important development goals in semiconductor memory technology is to embody ever smaller memory cells, i.e. to use ever smaller silicon areas per stored information unit (bit). The problem arises thereby that, on the one hand, the spatial extent of the charge trapped in a dielectric storage layer, which is approximately 40 nm, becomes larger and larger relative to the decreasing effective channel length of the memory transistor and, on the other hand, as the number of write and erase cycles increases, the stored charge tends to diffuse apart. Moreover, it is advantageous for the miniaturization sought if it is possible to reduce the required source-drain voltage for the operation of the memory cell. This voltage, at least in the case of programming by CHE (Channel Hot Electron), is largely predetermined by material-specific properties such as the electrical barrier height. It is approximately 3.1 eV for the customary layer combination of SiO
2
/Si
3
N
4
/SiO
2
. A reduction through suitable new layer combinations is therefore sought.
A memory cell of the kind described below is suitable for stand-alone applications and for so-called embedded applications. Memory cells having a dielectric adhesion layer as storage layer are known per se. The memory cell according to the invention as described below also has a layer construction which comprises a dielectric adhesion layer as storage layer. Such memory cells can be used e.g. in a virtual ground NOR architecture, known per se, or in a common ground NOR architecture. They can be programmed e.g. by channel hot electrons and erased by hot holes.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a fabrication method and an EEPROM memory cell configuration, which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which specifies a method for the fabrication and a construction of a memory cell which enable further miniaturization of the memories.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of fabricating a memory cell of an EEPROM. The method comprises:
forming a source region and a drain region, with a channel region therebetween, in semiconductor material; and
applying a three-layered layer structure with a storage layer between boundary layers and a gate electrode above the channel region, by performing the following steps:
in a first step, applying on a top side of a semiconductor material (body or semiconductor layer) a first boundary layer, an etching layer, a second boundary layer, and a gate electrode, whereby a material of the etching layer is selectively etchable with respect to a material of the first boundary layer and a material of the second boundary layer;
in a second step, removing at least the second boundary layer and the etching layer outside a region provided for the memory cell;
in a third step, selectively removing portions of the etching layer by a laterally effected etching attack under the second boundary layer, to form of the etching layer a residual portion above the channel region between the source region and the drain region;
in a fourth step, filling at least those regions below the second boundary layer wherein the material of the etching layer was removed with a material for a storage layer; and
subsequently processing further method steps for electrically connecting the resulting memory cell.
In accordance with an added feature of the invention, the second step comprises fabricating spacer elements on the two sides of the gate electrode facing the source region and the drain region, respectively, the spacer elements defining a projected lateral extent of the three-layered layer structure, and removing the second boundary layer, the etching layer, and the first boundary layer outside a region covered by the gate electrode and the spacer elements.
In accordance with an alternative feature of the invention, the second step comprises fabricating spacer elements on the two sides of the gate electrode facing the source region and the drain region, respectively, the spacer elements defining a projected lateral extent of the second boundary layer, and removing the second boundary layer and the etching layer outside a region covered by the gate electrode and the spacer elements.
In accordance with a further feature of the invention, the second step comprises removing the second boundary layer and the etching layer outside a region covered by the gate electrode, and between the fourth and fifth steps, fabricating spacer elements on the two sides of the gate electrode facing the source region and the drain region, respectively.
In accordance with an added feature of the invention, the first boundary layer is fabricated from SiO
2
, zirconium silicate, or hafnium silicate, the etching layer comprises Al
2
O
3
, and the second boundary layer is fabricated from SiO
2
, zirconium silicate, or hafnium silicate.
In accordance with a concomitant feature of the invention, the boundary layers is fabricated from zirconium silicate or hafnium silicate with an atomic layer deposition process (ALD).
With the above and other objects in view there is also provided, in accordance with the invention, a memory cell of an EEPROM, comprising:
a semiconductor material having a source region and a drain region formed therein;
a channel region between the source region and the drain region;
a three-layered layer structure formed above the channel region and a gate electrode above the layer structure, the layer structure having boundary layers and a storage layer between the boundary layer; and
an interruption of the storage layer above the channel region formed of a region of Al
2
O
3
between the boundary layers.
In other words, the memory cell comprises a source region and a drain region in semiconductor material and, above a channel region provided between the source and drain regions, a three-layered layer structure with a storage layer between boundary layers and a gate electrode arranged thereon, the storage layer being interrupt ed above the channel region and replaced by an etching layer made, preferably, of Al
2
O
3
. During the fabrication, a three-layered layer structure comprising a first boundary layer, which is preferably silicon dioxide, an etching layer, which is preferably Al
2
O
3
, and a second boundary layer, which is preferably likewise SiO
2
, is applied. In preferred embodiments, the boundary layers may alternatively be zirconium silicate or hafnium silicate.
The middle layer is etched out laterally in each case proceeding from the regions of the source and drain, so that the second boundary layer is undercut. The interspaces produced in this way are filled with the material provided for the storage layer, preferably silicon nitride. The provision of suitable spacer elements makes it possible to define the dimensions of the memory cell in an envisaged manner.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for the fabrication and construction of a memory cell, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.


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