Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-12-05
2006-12-05
Sarkar, Asok K. (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S245000, C438S246000, C257SE21651
Reexamination Certificate
active
07144770
ABSTRACT:
The invention provides a method for fabricating a memory cell, a substrate (101) being provided, a trench-type depression (102) being etched into the substrate (101), a barrier layer (103) being deposited non-conformally in the trench-type depression (102), grain elements (104) being grown on the inner areas of the trench-type depression (102), a dielectric layer (202) being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements (104) growing selectively on the inner areas (105) of the trench-type depression (102) in an electrode region (301) forming a lower region of the trench-type depression (102) and an amorphous silicon layer continuing to grow in a collar region (302) forming an upper region of the trench-type depression (102).
REFERENCES:
patent: 6027967 (2000-02-01), Parekh et al.
patent: 6297088 (2001-10-01), King
patent: 10234 735 (2004-02-01), None
patent: 0980 100 (1999-08-01), None
patent: WO 2004/017394 (2004-02-01), None
German Office Action dated Aug. 27, 2004.
Birner Albert
Foerster Matthias
Hecht Thomas
Orth Andreas
Stadtmueller Michael
Infineon - Technologies AG
Jenkins Wilson Taylor & Hunt, P.A.
Sarkar Asok K.
Yevsikov Victor V.
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