Memory cell array with a self-aligned, buried bit line

Details Memory cell array with a self-aligned, buried bit line Memory cell array with a self-aligned, buried bit line

1996-11-25

1998-05-19

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438244, 438564, 438675, H01L 218242

Patent

active

057535515

ABSTRACT:
A method for forming memory cells, featuring a bit line, embedded in an insulator filled, shallow trench, has been developed. Self-alignment of the buried bit line, to a source and drain region of a transfer gate transistor, is obtained via outdiffusion of a doped polysilicon layer, used as part of the buried bit line, composite layer.

REFERENCES:
patent: 5156993 (1992-10-01), Su
patent: 5250457 (1993-10-01), Dennison
patent: 5364808 (1994-11-01), Yang et al.
patent: 5369048 (1994-11-01), Hsue
patent: 5438009 (1995-08-01), Yang et al.
patent: 5441908 (1995-08-01), Lee et al.

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