Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-12-23
2000-06-27
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438529, H01L 218247
Patent
active
060806265
ABSTRACT:
A memory cell of the EEPROM type formed on a semiconductor material substrate having a first conductivity type includes a drain region having a second conductivity type and extending at one side of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region. The region of electric continuity is produced by implantation at a predetermined angle of inclination.
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Bottini Roberta
Cremonesi Carlo
Dalla Libera Giovanna
Vajana Bruno
Galanthay Theodore E.
Hack Jonathan
Niebling John F.
SGS--Thomson Microelectronics S.r.l.
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