Memory cell fabrication employing an interpoly gate dielectric a

Details Memory cell fabrication employing an interpoly gate dielectric a Memory cell fabrication employing an interpoly gate dielectric a

1997-10-22

1999-03-30

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438263, H01L 21336

Patent

active

058888705

ABSTRACT:
A method is provided for forming a non-volatile memory cell in which the upper surface of the floating gate is polished to reduce surface irregularities, providing for the formation of a gate dielectric having a relatively high breakdown voltage thereon. According to an embodiment, a first gate dielectric is thermally grown upon a semiconductor substrate which later serves as the tunnel dielectric in the ensuing memory cell. A floating gate polysilicon is deposited across the first gate dielectric, followed by ion implantation of dopants and nitrogen therein. The upper surface of the floating gate polysilicon is then polished using, e.g., CMP. A second gate dielectric comprising high quality oxynitride may then be thermally grown across the polished surface of the floating gate polysilicon. Alternately, a ceramic having a relatively high dielectric constant may be formed across the floating gate polysilicon to serve as the second gate dielectric. A control gate polysilicon may be formed across the second gate dielectric. After doping the control gate polysilicon, portions of the layers formed above the substrate may be removed to define sidewall surfaces of a stacked structure. Source and drain regions which are self-aligned to the sidewall surfaces of the stacked structure may then be formed within the substrate.

REFERENCES:
patent: 4774197 (1988-09-01), Haddad et al.
patent: 4789883 (1988-12-01), Cox et al.
patent: 5437762 (1995-08-01), Ochiai et al.
patent: 5445984 (1995-08-01), Hong et al.
patent: 5654219 (1997-08-01), Huber
patent: 5696015 (1997-12-01), Hwang
patent: 5739566 (1998-04-01), Ota
patent: 5759894 (1998-06-01), Tseng et al.

Affiliated with

Also associated with

Rating

Memory cell fabrication employing an interpoly gate dielectric a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory cell fabrication employing an interpoly gate dielectric a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory cell fabrication employing an interpoly gate dielectric a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1214316