Memory array with surrounding gate access transistors and...

Details Memory array with surrounding gate access transistors and... Memory array with surrounding gate access transistors and...

2009-02-27

2010-11-23

Dang, Phuc T (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S268000, C257S302000, C257S401000

Reexamination Certificate

active

07838360

ABSTRACT:
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.

REFERENCES:
patent: 7091566 (2006-08-01), Zhu et al.
patent: 7510954 (2009-03-01), Forbes

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