2F-square memory cell for gigabit memory applications

Details 2F-square memory cell for gigabit memory applications 2F-square memory cell for gigabit memory applications

1998-01-26

2000-03-21

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438242, 438245, 438263, 438266, 438270, H01L 218249, H01L 29788

Patent

active

060402105

ABSTRACT:
A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, each having a channel formed between source and drain regions. Two transistors are formed per pillar. This is achieved by forming two gates per pillar formed on opposite pillar sidewalls which are along the bitline direction. This forms two wordlines or gates per pillar arranged in the wordline direction. The source regions are self-aligned and located below the pillars. The source regions of adjacent bit lines are isolated from each other without increasing the cell size.

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