Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1995-09-22
2001-12-18
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S218000, C438S225000, C438S227000, C438S228000, C438S229000, C438S230000, C438S231000, C438S232000, C438S301000, C438S303000, C438S305000, C438S306000, C438S307000, C438S217000
Reexamination Certificate
active
06331458
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the manufacture of an integrated circuit and more particularly to an active area implant which improves MOSFET performance in NMOS and PMOS devices.
2. Description of the Relevant Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline material or “polysilicon” material over a relatively thin gate oxide, and implanting the polysilicon and adjacent source/drain regions with an impurity dopant material. If the impurity dopant material used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (“NMOS”) device. Conversely, if the source/drain dopant material is p-type, then the resulting MOSFET device is a PMOSFET (“PMOS”) device.
The polysilicon and adjacent source/drain regions are formed using well known photolithography techniques. Polysilicon and source/drain regions are patterned in openings formed through a thick layer of what is commonly referred to as “field oxide”. The openings are areas in which NMOS and PMOS devices are formed and, since they receive fabricated active devices, are generally called “active regions”. The active regions are therefore regions between field oxide and generally include gate oxide, polysilicon over gate oxide and source/drain regions formed within silicon on opposing sides of the polysilicon. Metal interconnect is routed over the thick field oxide to connect with the polysilicon as well as to the source/drain regions to complete the formation of an overall circuit structure.
Many circuits utilize both PMOS and NMOS devices on the same monolithic substrate. While both types of devices can be formed, the devices are distinguished based on the source/drain impurity dopant. The method by which n-type dopant is used to form an NMOS device and p-type dopant is used to form a PMOS device entails unique problems associated with each device. As MOSFET layout densities increase, the problems are exacerbated. Device failure can occur unless adjustments are made to processing parameters and processing steps. NMOS processing must, in many instances, be dissimilar from PMOS processing due to the unique problems of each type of device. Problems inherent in NMOS fabrication will be discussed first followed by PMOS second.
NMOS devices generally suffer from so-called “hot-carrier effects” to a greater degree than PMOS devices. Channel lengths smaller than, for example, 1.5 &mgr;m, make more severe the migration of hot carriers (i.e., electrons) to unwanted areas of the NMOS devices. Hot electrons in NMOS devices are more mobile than counterpart hot holes in PMOS devices making hot carrier effects a predominant problem in NMOS processing.
Hot electrons migrate not only as dimensions shrink in the channel but also as gate oxides become thinner and junctions become shallower. High electric fields allow migrating electrons to gain kinetic energy and become “hot”. Each hot electron can (i) cause impact ionization for generating electron-hole pairs in the channel region, and (ii) cause hot electrons to inject primarily from the channel region near the drain and into the overlying gate oxide. Impact ionization can precipitate inadvertent turn-on between the source and drain as the electron-hole pairs become free carriers and flow in opposite direction therebetween. Gate oxide injection can bias the gate oxide causing not only threshold shift but, in the extreme, latchup.
Numerous techniques are used to reduce the problems of hot electron injection in NMOS devices. See, e.g., Ng, et al. “Suppression of Hot-Carrier Degradation in Si MOSFET's by Germanium Doping”,
IEEE Electron Dev. Lett.,
Vol. 11, No. 1, (January, 1990). One technique includes a threshold implant adjust within the active region. Threshold adjust generally involves implanting a p-type dopant through the sacrificial oxide or gate oxide and into the underlying channel region. The p-type dopant typically used is boron having an atomic mass of 11 a.m.u. P-type boron thereby acts to increase the threshold of the NMOS device by increasing the concentration of p-type dopant at the surface near the silicon/gate oxide interface. Increase in p-type dopant in the channel in an NMOS device positively skews the threshold and reduces the likelihood of inadvertent turn-on, punch through, and latchup.
Light atomic mass associated with boron, while suitable as a threshold adjust dopant, can present additional problems unique to NMOS devices. For example, because of its low mass, boron has a tendency to segregate and migrate from its implanted position in the channel region to adjacent source/drain regions subsequently doped with heavier n-type ions. For example, if arsenic is used as the source/drain dopant, arsenic will inherently disrupt the lattice structure of the silicon substrate causing bond opportunities within the source/drain regions. The bond opportunities act as a sink for highly mobile, light boron atoms to move from their channel region to the adjacent source/drain regions thereby depleting threshold adjust effectiveness. Boron segregation and diffusion is believed by the present inventors to occur primarily at the edges of the channel, where the channel abuts against the source and drain periphery. A gradient of boron concentration thereby exists across the channel region, resulting from a lowering of threshold adjust dopant at the channel edges. As NMOS channel lengths are reduced, threshold reduction problems are compounded.
In addition to boron segregation and diffusion in lateral directions to adjacent source/drain regions, boron can also diffuse, due to its highly mobile characteristic, in a perpendicular direction to the overlying gate oxide. During subsequent thermal cycles, boron can easily move along interstitial or substitutional locations through the silicon/gate oxide interface. Perpendicular-moving boron is therefore consumed by a growing oxide to not only reduce boron concentration in the channel but, in the converse, is postulated to increase hole concentration in the gate oxide. Hole concentration increase in the gate oxide can attract injected electrons normally arising from hot electron effects. Attraction of hot electrons further compounds the problems of hot electron effects described above.
The deficiencies of boron as a threshold adjust is but one example of recognized problems in NMOS manufacture. Like NMOS, PMOS fabrication also entails numerous problems. The problems generally arise when gate lengths are shortened and are classified or categorized generally as short-channel effects (“SCEs”). To minimize SCEs in PMOS devices, researchers have indicated a need for maintaining the integrity of the channel region vis-a-vis the source/drain region. As taught in U.S. Pat. No. 4,835,112, various barrier dopants are used to retard and substantially prevent diffusion of the source/drain regions into the channel region beyond an initial target amount. Barrier ions such as germanium are typically implanted into the source/drain regions to retard lateral diffusion of the source/drain regions and maintain an effective channel length (Leff) of the PMOS device.
Maintaining integrity of the channel region, its size and dopant concentration, is essential in predicting PMOS operability. During formation of the p-type source/drain regions, p-type dopant is introduced in the self-aligned process across the active region, i.e., across the source/drain regions as well as into the polysilicon material overlying the channel region. If the p-type source/drain implant comprises boron or boron difluoride (BF
2
), then boron, due to its low atomic mass, has a tendency to migrate through the polysilicon gate material and enter the channel during subsequent anneal. See, e.g., Baker, et al., “The Influence of Fluorine on Threshold Voltage Instabilities in P+ Polysilicon Gated P-Channel MOSFETS,”
IEDM
(1989), pp. 443-446. Boron or boron difluoride derivatives causes a change in the concentration level of the
Anjum Mohammed
Burki Ibrahim K.
Stuber Alan L.
Advanced Micro Devices , Inc.
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Gurley Lynne A.
Niebling John F.
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