Abrupt source/drain extensions for CMOS transistors

Details Abrupt source/drain extensions for CMOS transistors Abrupt source/drain extensions for CMOS transistors

2002-09-26

2004-06-01

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S487000

Reexamination Certificate

active

06743687

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing semiconductor devices with sub-micron dimensions. The present invention has particular applicability in manufacturing high density semiconductor devices with CMOS transistors having abrupt, highly concentrated shallow source/drain extensions.
BACKGROUND ART
The increasing demand for micro-miniaturization requires scaling down various horizontal and vertical dimensions in various device structures. As the thickness of the ion implanted source/drain junctions of transistors is scaled down, there is a corresponding scaled increase in the substrate channel doping in order to maintain a constant electric field in the transistor channel for higher speed performance. These objectives are achieved, in part, by not only forming shallow junctions but also forming source/drain extensions with an abrupt junction/dopant profile slope in proximity to the transistor channel in order to reduce penetration of the source/drain dopant into the transistor channel which occurs as the junction/profile slope becomes less abrupt. Such short channel effects result in poor threshold voltage roll-off characteristics for sub-micron devices.
As the transistor dimensions plunge into the deep sub-micron regime, it becomes increasingly more difficult to form shallow source/drain extensions with abrupt junctions and a hight impurity concentration for reduced series resistance. It also becomes increasingly more difficult to form shallow source/drain extensions without adverse dopant diffusion and deactivation.
Accordingly, there exists a continuing need for a methodology enabling the fabrication of semiconductor devices containing transistors with abrupt source/drain extension junction profiles having a high impurity concentration without dopant deactivation.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device comprising CMOS transistors exhibiting reduced short channel effects and having high concentration shallow, abrupt source/drain extensions without dopant deactivation.
Additional advantages and other features of the present invention will be set forth in the description which follows and, in part, will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a gate electrode, having side surfaces, over a main surface of a semiconductor substrate with a gate dielectric layer therebetween; forming first sidewall spacers on the side surfaces of the gate electrode; ion implanting to form deep source/drain implants; annealing to activate deep source/drain regions; removing the first sidewall spacers; ion implanting to form shallow pre-amorphized regions between the deep source/drain regions and the gate electrode; ion implanting impurities into the shallow pre-amorphized regions to form shallow source/drain implants; and laser thermal annealing to crystallize the shallow pre-amorphized regions to activate shallow source/drain extensions.
Embodiments of the present invention include forming an oxide liner on the side surfaces of the gate electrode and on a portion of the main surface of the semiconductor substrate, forming nitride sidewall spacers, as the first sidewall spacers, on the oxide liner, forming deep source/drain regions, forming metal silicide layers on the main surface of the semiconductor substrate over the deep source/drain regions, removing the nitride sidewall spacers and oxide liner, and then forming the shallow pre-amorphized regions and shallow source/drain implants. Embodiments of the present invention further include forming second laser transparent sidewall spacers, such as silicon oxide sidewall spacers, on the side surfaces of the gate electrode, depositing a layer of laser reflective material, such as silicon nitride, over the semiconductor substrate after forming the second laser transparent oxide sidewall spacers, planarizing, as by chemical-mechanical polishing (CMP) such that an upper surface of the silicon nitride laser reflective material is substantially coplanar with the upper surface of the silicon oxide sidewall spacers, and then impinging a laser light beam through the second silicon oxide sidewall spacers to crystallize the shallow pre-amorphized regions and to activate the source/drain extensions. In accordance with embodiments of the present invention, laser thermal annealing may be implemented by impinging a pulsed laser light beam at a radiant fluence of 0.2 to 0.8 joules/cm
2
for 1 to 10 nanoseconds, thereby elevating the temperature of the pre-amorphized regions to 1,200° C. to 1,300° C.
Additional advantages of the present invention will be readily apparent to those skilled in the art from the following detailed description wherein the embodiments of the present invention are described simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, not as restrictive.


REFERENCES:
patent: 6335253 (2002-01-01), Chong et al.
patent: 6355543 (2002-03-01), Yu
patent: 6391731 (2002-05-01), Chong et al.
patent: 6514840 (2003-02-01), Barrett et al.

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