Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-07
2003-04-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06544828
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improving endurance of a high voltage memory device in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, shallow trench isolation (STI) is often used to isolate active areas from one another, especially in advanced CMOS technology with below 0.25 &mgr;m feature sizes. Then a gate oxide layer is formed in the active areas and semiconductor device structures fabricated. The gate oxide on the edge of the STI region is weaker and has a stronger electric field than the gate oxide in other areas. This can lead to reduced endurance of high voltage NMOS, especially in non-volatile memory devices such as EPROM, EEPROM, and Flash memories. It is desired to improve the product endurance and increase robustness of the NMOS devices.
U.S. Pat. No. 6,118,152 to Yamaguchi et al, 5,817,570 to Kerber et al, U.S. Pat No. 5,451,535 to Chan et al, U.S. Pat. No. 5,639,676 to Hshieh et al, and U.S. Pat. No. 5,376,578 to Hsu et al teach various field plate conductors. U.S. Pat. No. 5,340,768 to Gill shows a field plate conductor extending over a LOCOS region between row lines of a memory array.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method for increasing the endurance of gate oxide at the edge of an isolation region in the fabrication of integrated circuits.
It is a further object of the invention to improve the endurance and robustness of high voltage NMOS devices.
Yet another object is to provide a method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of an isolation region.
A still further object is to provide a method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of an isolation region on the drain side only.
Yet another object is to provide a method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of a shallow trench isolation region at the drain side only.
In accordance with the objects of the invention, a method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of a shallow trench isolation region at the drain side only is achieved. Active areas are separated by isolation regions in a substrate. A gate oxide layer is grown on the active areas. A conducting layer is deposited overlying the gate oxide layer and patterned to form gate electrodes in the active areas and to form conductive strips overlapping both the active areas and the isolation areas at an isolation's edge on a drain side of the active areas wherein the conductive strips reduce the electric field at the isolation's edge in the fabrication of an integrated circuit device.
REFERENCES:
patent: 5340768 (1994-08-01), Gill
patent: 5376578 (1994-12-01), Hsu et al.
patent: 5451535 (1995-09-01), Chan et al.
patent: 5639676 (1997-06-01), Hshieh et al.
patent: 5817570 (1998-10-01), Kerber et al.
patent: 5963480 (1999-10-01), Harari
patent: 6339243 (2000-03-01), Kwon et al.
patent: 6118152 (2000-09-01), Yamaguchi et al.
patent: 6468849 (2002-10-01), Efland et al.
Chu Wen-Ting
Hsieh Chia-Ta
Kuo Di-Son
Lin Chrong-Jung
Tsaur Sheng-Wei
Ackerman Stephen B.
Le Thao
Pike Rosemary L. S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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