Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-15
2002-05-21
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S528000, C438S487000
Reexamination Certificate
active
06391731
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming MOS transistors with shallow junctions using laser annealing in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
Sub-0.1 micron MOS technology requires the use of abrupt, ultra-shallow junctions for deep source and drains and for source and drain extensions. Traditional processing approaches have used ion implantation followed by rapid thermal annealing (RTA) to activate the implanted ions. However, RTA may not be capable for sub-0.1 micron technology because the RTA thermal ramp-up and ramp-down times are too large and can cause too much diffusion in the substrate. Furthermore, in some cases, two RTA cycles are required: one to form the source and drain extension and one to form the deep source and drain.
Several prior art approaches disclose methods to form source and drain junctions in the manufacture of integrated circuit devices. U.S. Pat. No. 5,998,272 to Ishida et al teaches a method to form salicide and deep source-drain regions prior to source-drain extension formation. A laser doping process is used in one embodiment. U.S. Pat. No. 5,937,325 to Ishida discloses a method to form silicide on an MOS gate. A titanium layer is deposited. A laser anneal is performed to form silicide. After removing unreacted metal, an RTA is performed to decrease the resistivity of the silicide. U.S. Pat. No. 5,966,605 to Ishida teaches a method to activate ions in the polysilicon gate. An ion implant is performed to dope the gate and the source and drain regions. A laser anneal is performed on the polysilicon gate but the unactivated ions do not diffuse in the source and drain regions. An RTA is then performed to activate the source and drain ions. U.S. Pat. No. 5,770,486 to Zhang et al and U.S. Pat. No. 5,891,766 to Yamazaki et al disclose methods to form thin film transistors. A laser anneal is used on the lightly doped drain (LDD) region. Related U.S. patent application Ser. No. 09/614557 (CS-00-003/004) to Y. F. Chong et al filed on Jul. 12, 2000, discloses a method to form transistors wherein a pre-amorphization implant and a laser anneal are used in conjunction with a spacer overetch.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method to form MOS transistors in the manufacture of an integrated circuit device.
A further object of the present invention is to attain excellent doping profile and activation control for ultra-shallow source and drain extensions and deep source and drain junctions.
A yet further object of the present invention is to replace rapid thermal anneal (RTA) activation with laser annealing.
A still yet further object of the present invention is to improve dopant profile control by using a pre-amorphization ion implant and a laser anneal.
A further object of the present invention is to simultaneously activate shallow source and drain extensions and deep source and drain junctions using a single laser anneal.
In accordance with the objects of this invention, a new method of forming MOS transistors with shallow source and drain extensions and deep source and drain junctions in the manufacture of an integrated circuit device has been achieved. Gates are provided overlying a semiconductor substrate. Each gate comprises a gate oxide layer overlying the semiconductor substrate and a polysilicon layer overlying the gate oxide layer. Temporary sidewall spacers are formed on the gates. Ions are implanted into the exposed semiconductor substrate to form a deep amorphous layer. Ions are implanted into the deep amorphous layer to form pre-annealed source and drain junctions. The temporary sidewall spacers are removed. Ions are implanted into the exposed semiconductor substrate to form a shallow amorphous layer. Ions are implanted into the shallow amorphous layer to form pre-annealed source and drain extensions. A capping layer may be deposited overlying the semiconductor substrate and the gates to protect the semiconductor substrate during irradiation. The semiconductor substrate is irradiated with laser light to melt the amorphous layer while the crystalline regions of the semiconductor substrate remain in solid state. Ions in the pre-annealed source and drain junctions diffuse into the deep amorphous layer while ions in the pre-annealed source and drain extensions diffuse into the shallow amorphous layer. The source and drain junctions and the source and drain extensions for the transistors are thereby simultaneously formed to complete the MOS transistors.
REFERENCES:
patent: 5770486 (1998-06-01), Zhang et al.
patent: 5891766 (1999-04-01), Yamazaki et al.
patent: 5937325 (1999-08-01), Ishida
patent: 5966605 (1999-10-01), Ishida
patent: 5998272 (1999-12-01), Ishida et al.
patent: 6225176 (2001-05-01), Yu
patent: 6297115 (2001-10-01), Yu
Chong Yung Fu
Pey Kin Leong
See Alex
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Schnabe Douglas R.
Tsai Jey
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