3-D CMOS transistors with high ESD reliability

Details 3-D CMOS transistors with high ESD reliability 3-D CMOS transistors with high ESD reliability

1998-03-23

1999-03-02

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438218, 438412, 438423, H01L 218238, H01L 2176

Patent

active

058770488

ABSTRACT:
The present invention discloses a method for manufacturing 3-D transistors with high electrostatic discharge (ESD) reliability. Pad oxide layers are on a silicon substrate and a thick field oxide is on the silicon substrate between the pad oxide layer. An oxygen amorphized region is formed in the substrate by using an ion implantation having oxygen ions as dopants and the field oxide as a hard mask. A high-temperature thermal annealing is implemented to convert the oxygen amorphized region into an oxygen implant-induced oxide regions. Then, the pad oxide layers and the field oxide are removed to form a field oxide region on the substrate and silicon islands on the oxygen implant-induced oxide regions. A thin gate oxide is deposited on the surface of the substrate and the silicon islands to seal the silicon islands. Finally, PMOSFETs are formed on the silicon islands and bulk NMOSFET buffers are formed on the field oxide region of the substrate.

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patent: 5795800 (1998-08-01), Chan et al.
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S. Maeda et al., Suppression of Delay Time Instability on Frequency using Field Shield Isolation Technology for Deep Sub-Micron SOI Circuits, 1996 IEEE, pp. 129-132.
J.A. Babcock et al., Low-Frequency Noise Dependence of TFSOI BiCMOS for Low Power RF Mixed-Mode Applications, 1996 IEEE, pp. 133-136.
Mansun Chan et al., ESD Reliability and Protection Schemes in SOI CMOS Output Buffers, IEEE Transductions on Electron Devices, vol. 42, No. 10, Oct. 1995, pp. 1816-1821.

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