3-D CMOS-on-SOI ESD structure and method

Details 3-D CMOS-on-SOI ESD structure and method 3-D CMOS-on-SOI ESD structure and method

1999-02-05

2000-06-13

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438199, 438200, H01L 2100, H01L 2184

Patent

active

060748990

ABSTRACT:
Three-dimensional ESD structures are constructed in SOI technology that utilize both bulk devices and thin film SOI devices.

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