Ultra high-speed chip interconnect using free-space dielectrics
Ultra low k plasma CVD nanotube/spin-on dielectrics with...
Ultra thin FET
Ultra thin, single phase, diffusion barrier for metal...
Ultra-late programming ROM and method of manufacture
Ultra-low loop wire bonding
Ultra-low temperature Al fill for sub-0.25 .mu.m generation of I
Ultra-thick metal-copper dual damascene process
Ultra-thin resist and silicon/oxide hard mask for metal etch
Ultra-uniform silicides in integrated circuit technology
Ultrathin chemically grown oxide film as a dopant diffusion...
Under bump metallization pad and solder bump connections
Under bump metallurgy structural design for high reliability...
Under-bump metallization layers and electroplated solder...
Undercut-free BLM process for Pb-free and Pb-reduced C4
Underfill process for flip-chip device
Underlayer film for copper, and a semiconductor device...
Underlayer liner for copper damascene in low k dielectric
Underlayer process for high O.sub.3 /TEOS interlayer dielectric
Underlayer protection for the dual damascene etching