Ultra thin FET

Details Ultra thin FET Ultra thin FET

2011-06-07

2011-06-07

Lebentritt, Michael S (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S977000, C257SE21597, C257SE21600

Reexamination Certificate

active

07955969

ABSTRACT:
Processes are described for forming very thin semiconductor die (1 to 10 microns thick) in which a thin layer of the upper surface of the wafer is processed with junction patterns and contacts while the wafer bulk is intact. The top surface is then contacted by a rigid wafer carrier and the bulk wafer is then ground/etched to an etch stop layer at the bottom of the thin wafer. A thick bottom contact is then applied to the bottom surface and the top wafer carrier is removed. All three contacts of a MOSFET may be formed on the top surface in one embodiment or defined by the patterning of the bottom metal contact.

REFERENCES:
patent: 5004705 (1991-04-01), Blackstone
patent: 5591678 (1997-01-01), Bendik et al.
patent: 6331467 (2001-12-01), Brown et al.
patent: 2003/0203552 (2003-10-01), Blanchard
patent: 2005/0001268 (2005-01-01), Baliga
patent: 2006/0035442 (2006-02-01), Ilicali et al.

Affiliated with

Also associated with

Rating

Ultra thin FET does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ultra thin FET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ultra thin FET will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2637787