Underlayer liner for copper damascene in low k dielectric

Details Underlayer liner for copper damascene in low k dielectric Underlayer liner for copper damascene in low k dielectric

1999-11-01

2002-07-09

Gouoreau, George (Department: 1763)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S624000, C438S637000, C438S704000, C438S725000, C438S740000

Reexamination Certificate

active

06417106

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of integrated circuits with particular reference to damascene structures in low k dielectrics.
BACKGROUND OF THE INVENTION
The term damascene when used in connection with integrated circuit wiring, refers to the fact that a layer has been inlaid within a supporting medium, as opposed to being covered by it. The main advantage of this approach to wiring is that it is highly cost effective relative to conventional wiring. The word ‘damascene’ is derived from the city of Damascus where inlaid jewelry of this general format was first produced. Copper is the metal most widely used in damascene technology, because of its excellent electrical conductivity.
The basic process for forming a damascene structure is schematically illustrated in FIG.
1
. Dielectric layer
13
has been laid down on substrate
11
which in most cases would itself be a dielectric layer that covers a partially completed integrated circuit. Wiring for said integrated circuit is to be formed within
13
which serves as a separator between different wiring levels, hence the term IMD or inter metal dielectric. An etch stop layer such as layer
12
is placed between layers
11
and
13
to facilitate formation of trenches, such as
14
and
15
. These latter are then overfilled with copper (layer
16
) giving the structure the appearance seen in FIG.
1
.
Once the structure of
FIG. 1
has been formed, all excess copper outside the trenches is removed as part of a planarizing step (usually, but not necessarily, chemical mechanical polishing or CMP) to level the topmost surface of the IC in anticipation of the formation of a new wiring layer. Unfortunately, because it is an intrinsically soft material, the copper gets removed somewhat faster than the surrounding dielectric material and the result is dishing of the copper across the mouths of trenches as illustrated in FIG.
2
. Dishing is undesirable because it reduces the conductive cross-section of the wiring.
Various solutions have been proposed for minimizing the amount of dishing. For example, the planarization process may be terminated somewhat prematurely. Unfortunately this can result in a thin layer of copper being left behind on the surface of the dielectric. Other approaches have included placing a layer of a hard material immediately below and/or above the copper layer.
These various solutions to the dishing problem were developed for use with inorganic dielectric materials, such as silicon oxide. More recently, however, there has been a drive to replace these with dielectrics having lower dielectric constants, the so called low k dielectrics. For our purposes we will define a low k dielectric as one that has a dielectric constant less than about 3. Such materials are to be found in the realm of organic rather than inorganic compounds. Examples include hydrogen silsesquioxane, fluorinated polyimide, polyarylene ether, fluorinated arylene ether, polytetrafluoro-ethylene, and benzocyclobutene. Materials of this type are not, in general, as mechanically rigid as their inorganic counterparts so that the edges of the trenches tend to yield more to the stress of CMP thereby exacerbating the dishing problem. This additional contribution to the dishing effect is particularly noticeable in the case of many narrow trenches side by side (such as 15 in
FIG. 1
) as compared to isolated, wide trenches (such as
14
).
The present invention teaches a way to reduce dishing in low k (soft) dielectrics during CMP, particularly for multiple narrow trenches close together. In a search of the prior art we were unable to find any references that teach the method of the present invention. Some references were, however, found to be of interest. For example, in a non-damascene process, Boeck et al. (U.S. Pat. No. 5,880,018) initially use a high k dielectric and then replace portions of it with a low k dielectric in places where this is needed, such as at crossover points between wires.
Joshi et al. (U.S. Pat. No. 5,889,328) avoids the problem of dishing by using a damascene-like process that requires no planarization steps since the starting point is a planar surface and removal of excess material is performed by chemical etching. Cronin (U.S. Pat. No. 5,818,110) describes a damascene process that uses two etch stop layers but these are separated from one another by the dielectric layer. Nguyen et al. (U.S. Pat. No. 5,904,565) teach a method for making contact through the via hole in a dual damascene process. A key feature is the anisotropic etching of the barrier layer whereby it is preferentially removed between the two levels that need to make contact.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a process for the formation of a damascene structure.
Another object on the invention has been that said process result in a minimum of dishing at the surface of the structure.
A still further object has been that said damascene structure be formed in a dielectric layer of low dielectric constant.
These objects have been achieved by interposing a liner layer between the low k dielectric layer and the etch stop layer. The only requirement for the liner material is that it should have different etching characteristics from the etch stop material so that when trenches are etched in the dielectric they extend as far as the etch stop layer, in the normal way. When this is done it is found that dishing, after CMP, is significantly reduced particularly for trench structures made up of multiple narrow trenches spaced close together.


REFERENCES:
patent: 5818110 (1998-10-01), Cronin
patent: 5880018 (1999-03-01), Boeck et al.
patent: 5889328 (1999-03-01), Joshi et al.
patent: 5904565 (1999-05-01), Nguyen et al.
patent: 6054379 (2000-04-01), Yau et al.
patent: 6124200 (2000-09-01), Wang et al.
patent: 6184128 (2001-02-01), Wang et al.
patent: 6225204 (2001-05-01), Wu et al.
patent: 6331481 (2001-12-01), Stamper et al.
patent: 6372632 (2002-04-01), Yu et al.

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