Underlayer process for high O.sub.3 /TEOS interlayer dielectric

Details Underlayer process for high O.sub.3 /TEOS interlayer dielectric Underlayer process for high O.sub.3 /TEOS interlayer dielectric

1997-09-11

2000-02-15

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438622, 438626, 438631, 438761, 438778, 438787, 438791, 438958, H01L 214763

Patent

active

060252634

ABSTRACT:
A underlayer process for high O.sub.3 /TEOS interlayer dielectric deposition is disclosed. First, a layer of metal pattern is defined on a semiconductor substrate, then a layer of dielectric underlayer is deposited, next, a high O.sub.3 /TEOS interlayer dielectric is formed to achieve planarization. The key point of this process is to apply materials with higher refraction index than conventional PE-TEOS for forming interlayer dielectric underlayer. The mentioned material can be PE-SiH.sub.4 with a constant or decreasing refraction index with the distance from the semiconductor substrate. The underlayer can also be bi-layer structure consisting of high refraction index bottom layer and low refraction index surface layer. This invention can effectively suppress the problem caused from high surface sensitivity of O.sub.3 /TEOS, and improve the quality of interlayer dielectric planarization process dramatically.

REFERENCES:
patent: 4446194 (1984-05-01), Candelaria et al.
patent: 4908333 (1990-03-01), Shimokawa et al.
patent: 5252515 (1993-10-01), Tsai et al.
patent: 5744378 (1998-04-01), Homma
patent: 5766974 (1998-06-01), Sardella et al.

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